Lines Matching refs:ADDR
56 #define DUMMY_READ() smc->hw.mc_dummy = (u_short) inp(ADDR(B0_RAP))
264 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R1_CSR) ;
265 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R1_DA) ;
271 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R2_CSR) ;
272 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R2_DA) ;
294 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XS_CSR) ;
295 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XS_DA) ;
305 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XA_CSR) ;
306 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XA_DA) ;
773 smc->hw.fp.fm_st1u = (HW_PTR) ADDR(B0_ST1U) ;
774 smc->hw.fp.fm_st1l = (HW_PTR) ADDR(B0_ST1L) ;
775 smc->hw.fp.fm_st2u = (HW_PTR) ADDR(B0_ST2U) ;
776 smc->hw.fp.fm_st2l = (HW_PTR) ADDR(B0_ST2L) ;
777 smc->hw.fp.fm_st3u = (HW_PTR) ADDR(B0_ST3U) ;
778 smc->hw.fp.fm_st3l = (HW_PTR) ADDR(B0_ST3L) ;
817 outp(ADDR(B0_CTRL), CTRL_HPI_SET) ;
877 outpd(ADDR(B0_R1_CSR),CSR_SET_RESET) ;
878 outpd(ADDR(B0_XA_CSR),CSR_SET_RESET) ;
879 outpd(ADDR(B0_XS_CSR),CSR_SET_RESET) ;
880 outp(ADDR(B0_CTRL), CTRL_HPI_CLR) ;
881 outpd(ADDR(B0_R1_CSR),CSR_CLR_RESET) ;
882 outpd(ADDR(B0_XA_CSR),CSR_CLR_RESET) ;
883 outpd(ADDR(B0_XS_CSR),CSR_CLR_RESET) ;
885 outpd(ADDR(B4_R1_F), RX_WATERMARK) ;
886 outpd(ADDR(B5_XA_F), TX_WATERMARK) ;
887 outpd(ADDR(B5_XS_F), TX_WATERMARK) ;
1235 outpw(ADDR(B2_RTM_CRTL),TIM_CL_IRQ) ; /* clear IRQ */
1236 if (inpw(ADDR(B2_RTM_CRTL)) & TIM_RES_TOK) {
1243 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable RTM monitoring */
1248 outpd(ADDR(B2_RTM_INI),0) ; /* timer = 0 */
1249 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable IRQ */
1259 outpd(ADDR(B2_RTM_INI),smc->mib.a[PATH0].fddiPATHT_Rmode) ;