Lines Matching defs:PORT
114 #define PORT p->cmdr_addr
150 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);}
151 #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_DATAREG))
258 outw(80,PORT+L_ADDRREG);
259 if(inw(PORT+L_ADDRREG) != 80)
263 outw(0,PORT+L_ADDRREG);
264 outw((short)isa0,PORT+L_BUSIF); /* write ISA 0: DMA_R : isa0 * 50ns */
265 outw(1,PORT+L_ADDRREG);
266 outw((short)isa1,PORT+L_BUSIF); /* write ISA 1: DMA_W : isa1 * 50ns */
268 outw(CSR0,PORT+L_ADDRREG); /* switch back to CSR0 */
306 outw(inw(PORT+L_RESET),PORT+L_RESET); /* that's the hard way */
432 outw(inw(PORT+L_RESET),PORT+L_RESET); /* first: reset the card */
441 outw(88,PORT+L_ADDRREG);
442 if(inw(PORT+L_ADDRREG) == 88) {
444 v = inw(PORT+L_DATAREG);
446 outw(89,PORT+L_ADDRREG);
447 v |= inw(PORT+L_DATAREG);
571 if(inw(PORT+L_DATAREG) & (CSR0_IDON | CSR0_MERR) )
784 outw(inw(PORT+L_RESET),PORT+L_RESET); /* first: reset the card */
835 if(inw(PORT+L_DATAREG) & CSR0_IDON) {
841 printk(KERN_ERR "%s: can't init lance, status: %04x\n",dev->name,(int) inw(PORT+L_DATAREG));
863 csr0 = inw(PORT+L_DATAREG);
1041 dev->name,(int) rmdstat,csr0,(int) inw(PORT+L_DATAREG) );