Lines Matching refs:port_num
54 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr);
55 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr);
57 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
59 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
61 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
62 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
206 unsigned int port_num = mp->port_num;
208 eth_port_init_mac_tables(port_num);
209 eth_port_uc_addr_set(port_num, dev->dev_addr);
225 config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num));
230 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg);
291 eth_port_reset(mp->port_num);
462 int port_num = mp->port_num;
466 o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
489 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
492 queues = mv643xx_eth_port_disable_tx(port_num);
495 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
497 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
499 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
502 mv643xx_eth_port_enable_tx(port_num, queues);
523 unsigned int port_num = mp->port_num;
526 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
530 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
532 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
543 mv643xx_eth_port_enable_tx(port_num,
560 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
563 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
785 unsigned int port_num = mp->port_num;
790 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
791 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
793 mv_read (MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num));
799 port_num);
889 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
893 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
896 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
900 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
919 mv643xx_eth_port_disable_tx(mp->port_num);
937 unsigned int port_num = mp->port_num;
941 mv643xx_eth_port_disable_rx(port_num);
977 unsigned int port_num = mp->port_num;
980 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
982 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
990 eth_port_reset(mp->port_num);
1014 unsigned int port_num = mp->port_num;
1023 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1037 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1038 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1039 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1189 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
1258 int port_num = mp->port_num;
1260 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1262 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1266 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1313 int port_num;
1381 port_num = mp->port_num = pd->port_number;
1384 eth_port_uc_addr_get(port_num, dev->dev_addr);
1392 ethernet_phy_set(port_num, pd->phy_addr);
1417 mp->mii.phy_id = ethernet_phy_get(port_num);
1421 err = ethernet_phy_detect(port_num);
1425 port_num, ethernet_phy_get(port_num));
1429 ethernet_phy_reset(port_num);
1444 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1520 unsigned int port_num = mp->port_num;
1523 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
1524 mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1526 eth_port_reset(port_num);
1697 * port_num User Ethernet port number.
1749 eth_port_reset(mp->port_num);
1751 eth_port_init_mac_tables(mp->port_num);
1784 unsigned int port_num = mp->port_num;
1791 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1796 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1800 eth_port_uc_addr_set(port_num, dev->dev_addr);
1803 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num),
1806 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1809 pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
1812 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1820 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1823 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1826 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1830 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
1833 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1837 ethernet_phy_reset(mp->port_num);
1844 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr)
1854 mv_write(MV643XX_ETH_MAC_ADDR_LOW(port_num), mac_l);
1855 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(port_num), mac_h);
1858 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port_num);
1865 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr)
1870 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(port_num));
1871 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(port_num));
2019 unsigned int eth_port_num = mp->port_num;
2135 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2181 static int ethernet_phy_detect(unsigned int port_num)
2186 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2189 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2191 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2196 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2285 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
2288 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
2291 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
2294 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
2297 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2302 queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2306 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2311 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2316 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2324 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2329 queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2333 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2338 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2364 static void eth_port_reset(unsigned int port_num)
2368 mv643xx_eth_port_disable_tx(port_num);
2369 mv643xx_eth_port_disable_rx(port_num);
2372 eth_clear_mib_counters(port_num);
2375 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2379 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2391 * unsigned int port_num Ethernet Port number.
2403 static void eth_port_read_smi_reg(unsigned int port_num,
2406 int phy_addr = ethernet_phy_get(port_num);
2416 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2428 printk("mv643xx PHY read timeout, port %d\n", port_num);
2495 eth_port_read_smi_reg(mp->port_num, location, &val);
2502 eth_port_write_smi_reg(mp->port_num, location, val);