Lines Matching defs:dev_cap
104 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
186 dev_cap->reserved_qps = 1 << (field & 0xf);
188 dev_cap->max_qps = 1 << (field & 0x1f);
190 dev_cap->reserved_srqs = 1 << (field >> 4);
192 dev_cap->max_srqs = 1 << (field & 0x1f);
194 dev_cap->max_cq_sz = 1 << field;
196 dev_cap->reserved_cqs = 1 << (field & 0xf);
198 dev_cap->max_cqs = 1 << (field & 0x1f);
200 dev_cap->max_mpts = 1 << (field & 0x3f);
202 dev_cap->reserved_eqs = 1 << (field & 0xf);
204 dev_cap->max_eqs = 1 << (field & 0x7);
206 dev_cap->reserved_mtts = 1 << (field >> 4);
208 dev_cap->max_mrw_sz = 1 << field;
210 dev_cap->reserved_mrws = 1 << (field & 0xf);
212 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
214 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
216 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
218 dev_cap->max_rdma_global = 1 << (field & 0x3f);
220 dev_cap->local_ca_ack_delay = field & 0x1f;
222 dev_cap->num_ports = field & 0xf;
224 dev_cap->stat_rate_support = stat_rate;
225 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
227 dev_cap->reserved_uars = field >> 4;
229 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
231 dev_cap->min_page_sz = 1 << field;
236 dev_cap->bf_reg_size = 1 << (field & 0x1f);
238 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
240 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
242 dev_cap->bf_reg_size = 0;
247 dev_cap->max_sq_sg = field;
249 dev_cap->max_sq_desc_sz = size;
252 dev_cap->max_qp_per_mcg = 1 << field;
254 dev_cap->reserved_mgms = field & 0xf;
256 dev_cap->max_mcgs = 1 << field;
258 dev_cap->reserved_pds = field >> 4;
260 dev_cap->max_pds = 1 << (field & 0x3f);
263 dev_cap->rdmarc_entry_sz = size;
265 dev_cap->qpc_entry_sz = size;
267 dev_cap->aux_entry_sz = size;
269 dev_cap->altc_entry_sz = size;
271 dev_cap->eqc_entry_sz = size;
273 dev_cap->cqc_entry_sz = size;
275 dev_cap->srq_entry_sz = size;
277 dev_cap->cmpt_entry_sz = size;
279 dev_cap->mtt_entry_sz = size;
281 dev_cap->dmpt_entry_sz = size;
284 dev_cap->max_srq_sz = 1 << field;
286 dev_cap->max_qp_sz = 1 << field;
288 dev_cap->resize_srq = field & 1;
290 dev_cap->max_rq_sg = field;
292 dev_cap->max_rq_desc_sz = size;
294 MLX4_GET(dev_cap->bmme_flags, outbox,
296 MLX4_GET(dev_cap->reserved_lkey, outbox,
298 MLX4_GET(dev_cap->max_icm_sz, outbox,
302 for (i = 1; i <= dev_cap->num_ports; ++i) {
304 dev_cap->max_vl[i] = field >> 4;
306 dev_cap->max_mtu[i] = field >> 4;
307 dev_cap->max_port_width[i] = field & 0xf;
309 dev_cap->max_gids[i] = 1 << (field & 0xf);
311 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
319 for (i = 1; i <= dev_cap->num_ports; ++i) {
326 dev_cap->max_mtu[i] = field & 0xf;
328 dev_cap->max_port_width[i] = field & 0xf;
330 dev_cap->max_gids[i] = 1 << (field >> 4);
331 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
333 dev_cap->max_vl[i] = field & 0xf;
337 if (dev_cap->bmme_flags & 1)
340 dev_cap->bmme_flags, dev_cap->reserved_lkey);
349 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
350 dev_cap->reserved_eqs);
353 (unsigned long long) dev_cap->max_icm_sz >> 20);
355 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
357 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
359 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
361 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
363 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
365 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
367 dev_cap->max_pds, dev_cap->reserved_mgms);
369 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
371 dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu[1],
372 dev_cap->max_port_width[1]);
374 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
376 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
378 dump_dev_cap_flags(dev, dev_cap->flags);