Lines Matching refs:mace
32 #include <asm/ip32/mace.h>
104 mace->eth.mac_addr = (*(unsigned long*)o2meth_eaddr) >> 16;
111 while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
119 mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
121 mace->eth.phy_trans_go = 1;
190 mace->eth.mac_ctrl = priv->mac_ctrl;
199 mace->eth.mac_ctrl = priv->mac_ctrl;
213 mace->eth.tx_ring_base = priv->tx_ring_dma;
234 mace->eth.rx_fifo = priv->rx_ring_dmas[i];
272 mace->eth.mac_ctrl = SGI_MAC_RESET;
274 mace->eth.mac_ctrl = 0;
291 mace->eth.mac_ctrl = priv->mac_ctrl;
299 mace->eth.dma_ctrl = priv->dma_ctrl;
338 mace->eth.dma_ctrl = priv->dma_ctrl;
362 mace->eth.dma_ctrl = priv->dma_ctrl;
382 mace->eth.dma_ctrl = priv->dma_ctrl;
453 mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
459 mace->eth.dma_ctrl = priv->dma_ctrl;
460 mace->eth.int_stat = METH_INT_RX_THRESHOLD;
482 mace->eth.dma_ctrl = priv->dma_ctrl;
530 mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
552 mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
557 mace->eth.dma_ctrl = priv->dma_ctrl;
561 mace->eth.int_stat = METH_INT_ERROR;
573 status = mace->eth.int_stat;
592 status = mace->eth.int_stat;
686 mace->eth.tx_info = priv->tx_write;
701 mace->eth.dma_ctrl = priv->dma_ctrl;
714 mace->eth.dma_ctrl = priv->dma_ctrl;
747 mace->eth.dma_ctrl = priv->dma_ctrl;
804 dev->base_addr = (unsigned long)&mace->eth;
817 dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));