Lines Matching refs:iobase
288 static void SetMaxRxPacketSize(__u16 iobase, __u16 size)
294 WriteReg(iobase, I_CF_L_2, low);
295 WriteReg(iobase, I_CF_H_2, high);
303 static void SetFIFO(__u16 iobase, __u16 value)
307 WriteRegBit(iobase, 0x11, 0, 0);
308 WriteRegBit(iobase, 0x11, 7, 1);
311 WriteRegBit(iobase, 0x11, 0, 0);
312 WriteRegBit(iobase, 0x11, 7, 0);
315 WriteRegBit(iobase, 0x11, 0, 1);
316 WriteRegBit(iobase, 0x11, 7, 0);
319 WriteRegBit(iobase, 0x11, 0, 0);
320 WriteRegBit(iobase, 0x11, 7, 0);
414 static void SetTimer(__u16 iobase, __u8 count)
416 EnTimerInt(iobase, OFF);
417 WriteReg(iobase, TIMER, count);
418 EnTimerInt(iobase, ON);
422 static void SetSendByte(__u16 iobase, __u32 count)
429 WriteReg(iobase, TX_C_L, low);
430 WriteReg(iobase, TX_C_H, high);
434 static void ResetChip(__u16 iobase, __u8 type)
439 WriteReg(iobase, RESET, type);
442 static int CkRxRecv(__u16 iobase, struct via_ircc_cb *self)
447 low = ReadReg(iobase, RX_C_L);
448 high = ReadReg(iobase, RX_C_H);
452 low = ReadReg(iobase, RX_C_L);
453 high = ReadReg(iobase, RX_C_H);
463 static __u16 RxCurCount(__u16 iobase, struct via_ircc_cb * self)
468 low = ReadReg(iobase, RX_P_L);
469 high = ReadReg(iobase, RX_P_H);
479 static __u16 GetRecvByte(__u16 iobase, struct via_ircc_cb * self)
484 low = ReadReg(iobase, RX_P_L);
485 high = ReadReg(iobase, RX_P_H);
497 low=ReadReg(iobase,RX_C_L);
498 high=ReadReg(iobase,RX_C_H);
536 static void ActClk(__u16 iobase, __u8 value)
539 bTmp = ReadReg(iobase, 0x34);
541 WriteReg(iobase, 0x34, bTmp | Clk_bit);
543 WriteReg(iobase, 0x34, bTmp & ~Clk_bit);
546 static void ClkTx(__u16 iobase, __u8 Clk, __u8 Tx)
550 bTmp = ReadReg(iobase, 0x34);
557 WriteReg(iobase, 0x34, bTmp);
565 WriteReg(iobase, 0x34, bTmp);
568 static void Wr_Byte(__u16 iobase, __u8 data)
574 ClkTx(iobase, 0, 1);
577 ActClk(iobase, 1);
583 ClkTx(iobase, 0, 1); //bit data = 1;
585 ClkTx(iobase, 0, 0); //bit data = 1;
589 ActClk(iobase, 1); //clk hi
594 static __u8 Rd_Indx(__u16 iobase, __u8 addr, __u8 index)
600 ClkTx(iobase, 0, 0);
602 ActClk(iobase, 1);
604 Wr_Byte(iobase, bTmp);
606 ClkTx(iobase, 0, 0);
609 ActClk(iobase, 1);
611 ActClk(iobase, 0);
613 ClkTx(iobase, 0, 1);
615 bTmp = ReadReg(iobase, 0x34);
621 ActClk(iobase, 1);
623 ActClk(iobase, 0);
624 bTmp = ReadReg(iobase, 0x34);
634 ActClk(iobase, 1);
636 ActClk(iobase, 0);
639 bTmp = ReadReg(iobase, 0x34);
642 ActClk(iobase, 1);
644 ActClk(iobase, 0);
647 ClkTx(iobase, 0, 0);
650 ActClk(iobase, 1);
652 ActClk(iobase, 0);
658 static void Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data)
663 ClkTx(iobase, 0, 0);
665 ActClk(iobase, 1);
668 Wr_Byte(iobase, bTmp);
669 Wr_Byte(iobase, data);
671 ClkTx(iobase, 0, 0);
673 ActClk(iobase, 1);
676 ActClk(iobase, 0);
679 static void ResetDongle(__u16 iobase)
682 ClkTx(iobase, 0, 0);
685 ActClk(iobase, 1);
687 ActClk(iobase, 0);
690 ActClk(iobase, 0);
693 static void SetSITmode(__u16 iobase)
700 bTmp = ReadReg(iobase, 0x35);
701 WriteReg(iobase, 0x35, bTmp | 0x40); // Driver ITMOFF
702 WriteReg(iobase, 0x28, bTmp | 0x80); // enable All interrupt
705 static void SI_SetMode(__u16 iobase, int mode)
711 SetSITmode(iobase);
712 ResetDongle(iobase);
714 Wr_Indx(iobase, 0x40, 0x0, 0x17); //RX ,APEN enable,Normal power
715 Wr_Indx(iobase, 0x40, 0x1, mode); //Set Mode
716 Wr_Indx(iobase, 0x40, 0x2, 0xff); //Set power to FIR VFIR > 1m
717 bTmp = Rd_Indx(iobase, 0x40, 1);
720 static void InitCard(__u16 iobase)
722 ResetChip(iobase, 5);
723 WriteReg(iobase, I_ST_CT_0, 0x00); // open CHIP on
724 SetSIRBOF(iobase, 0xc0); // hardware default value
725 SetSIREOF(iobase, 0xc1);
728 static void CommonInit(__u16 iobase)
730 // EnTXCRC(iobase,0);
731 SwapDMA(iobase, OFF);
732 SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
733 EnRXFIFOReadyInt(iobase, OFF);
734 EnRXFIFOHalfLevelInt(iobase, OFF);
735 EnTXFIFOHalfLevelInt(iobase, OFF);
736 EnTXFIFOUnderrunEOMInt(iobase, ON);
737 // EnTXFIFOReadyInt(iobase,ON);
738 InvertTX(iobase, OFF);
739 InvertRX(iobase, OFF);
741 if (IsSIROn(iobase)) {
742 SIRFilter(iobase, ON);
743 SIRRecvAny(iobase, ON);
745 SIRFilter(iobase, OFF);
746 SIRRecvAny(iobase, OFF);
748 EnRXSpecInt(iobase, ON);
749 WriteReg(iobase, I_ST_CT_0, 0x80);
750 EnableDMA(iobase, ON);
753 static void SetBaudRate(__u16 iobase, __u32 rate)
757 if (IsSIROn(iobase)) {
780 } else if (IsMIROn(iobase)) {
782 } else if (IsFIROn(iobase)) {
785 temp = (ReadReg(iobase, I_CF_H_1) & 0x03);
787 WriteReg(iobase, I_CF_H_1, temp);
790 static void SetPulseWidth(__u16 iobase, __u8 width)
794 temp = (ReadReg(iobase, I_CF_L_1) & 0x1f);
795 temp1 = (ReadReg(iobase, I_CF_H_1) & 0xfc);
800 WriteReg(iobase, I_CF_L_1, temp);
801 WriteReg(iobase, I_CF_H_1, temp1);
804 static void SetSendPreambleCount(__u16 iobase, __u8 count)
808 temp = ReadReg(iobase, I_CF_L_1) & 0xe0;
810 WriteReg(iobase, I_CF_L_1, temp);