Lines Matching refs:iobase
33 * bank = inb(iobase+BSR);
37 * outb(bank, iobase+BSR);
170 static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase);
173 static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
174 static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase);
177 static int nsc_ircc_read_dongle_id (int iobase);
178 static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id);
331 * Function nsc_ircc_open (iobase, irq)
390 IRDA_WARNING("%s(), can't get iobase of 0x%03x\n",
503 int iobase;
509 iobase = self->io.fir_base;
536 * Function nsc_ircc_init_108 (iobase, cfg_base, irq, dma)
966 int iobase = info->fir_base;
969 switch_bank(iobase, BANK3);
970 version = inb(iobase+MID);
983 switch_bank(iobase, BANK2);
984 outb(ECR1_EXT_SL, iobase+ECR1);
985 switch_bank(iobase, BANK0);
988 switch_bank(iobase, BANK0);
989 outb(FCR_RXTH|FCR_TXTH|FCR_TXSR|FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
991 outb(0x03, iobase+LCR); /* 8 bit word length */
992 outb(MCR_SIR, iobase+MCR); /* Start at SIR-mode, also clears LSR*/
995 switch_bank(iobase, BANK2);
996 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
999 switch_bank(iobase, BANK5);
1000 outb(0x02, iobase+4);
1003 switch_bank(iobase, BANK6);
1004 outb(0x20, iobase+0); /* Set 32 bits FIR CRC */
1005 outb(0x0a, iobase+1); /* Set MIR pulse width */
1006 outb(0x0d, iobase+2); /* Set SIR pulse width to 1.6us */
1007 outb(0x2a, iobase+4); /* Set beginning frag, and preamble length */
1010 switch_bank(iobase, BANK0);
1011 outb(IER_RXHDL_IE, iobase+IER);
1023 static int nsc_ircc_read_dongle_id (int iobase)
1028 bank = inb(iobase+BSR);
1031 switch_bank(iobase, BANK7);
1034 outb(0x00, iobase+7);
1040 dongle_id = inb(iobase+4) & 0x0f;
1047 switch_bank(iobase, BANK0);
1049 outb(bank, iobase+BSR);
1055 * Function nsc_ircc_init_dongle_interface (iobase, dongle_id)
1062 static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id)
1067 bank = inb(iobase+BSR);
1070 switch_bank(iobase, BANK7);
1103 outb(0x28, iobase+7); /* Set irsl[0-2] as output */
1116 outb(0x48, iobase+7);
1119 outb(0x28, iobase+7); /* Set irsl[0-2] as output */
1125 switch_bank(iobase, BANK0);
1126 outb(0x62, iobase+MCR);
1134 outb(0x00, iobase+4);
1137 outb(bank, iobase+BSR);
1142 * Function nsc_ircc_change_dongle_speed (iobase, speed, dongle_id)
1147 static void nsc_ircc_change_dongle_speed(int iobase, int speed, int dongle_id)
1152 bank = inb(iobase+BSR);
1155 switch_bank(iobase, BANK7);
1186 outb(0x00, iobase+4);
1188 outb(0x01, iobase+4);
1191 outb(0x01, iobase+4);
1196 outb(0x81, iobase+4);
1197 outb(0x80, iobase+4);
1199 outb(0x00, iobase+4);
1215 switch_bank(iobase, BANK0);
1216 outb(0x62, iobase+MCR);
1222 outb(bank, iobase+BSR);
1236 int iobase;
1244 iobase = self->io.fir_base;
1250 bank = inb(iobase+BSR);
1253 switch_bank(iobase, BANK0);
1254 outb(0, iobase+IER);
1257 switch_bank(iobase, BANK2);
1259 outb(0x00, iobase+BGDH);
1261 case 9600: outb(0x0c, iobase+BGDL); break;
1262 case 19200: outb(0x06, iobase+BGDL); break;
1263 case 38400: outb(0x03, iobase+BGDL); break;
1264 case 57600: outb(0x02, iobase+BGDL); break;
1265 case 115200: outb(0x01, iobase+BGDL); break;
1267 switch_bank(iobase, BANK5);
1270 outb(inb(iobase+4) | 0x04, iobase+4);
1291 switch_bank(iobase, BANK0);
1292 outb(mcr | MCR_TX_DFR, iobase+MCR);
1295 nsc_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
1298 switch_bank(iobase, BANK0);
1299 outb(0x00, iobase+FCR);
1300 outb(FCR_FIFO_EN, iobase+FCR);
1306 iobase+FCR);
1309 switch_bank(iobase, BANK2);
1310 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
1313 switch_bank(iobase, BANK0);
1325 outb(ier, iobase+IER);
1328 outb(bank, iobase+BSR);
1344 int iobase;
1352 iobase = self->io.fir_base;
1388 bank = inb(iobase+BSR);
1398 switch_bank(iobase, BANK0);
1399 outb(IER_TXLDL_IE, iobase+IER);
1402 outb(bank, iobase+BSR);
1416 int iobase;
1422 iobase = self->io.fir_base;
1460 bank = inb(iobase+BSR);
1501 switch_bank(iobase, BANK4);
1502 outb(mtt & 0xff, iobase+TMRL);
1503 outb((mtt >> 8) & 0x0f, iobase+TMRH);
1506 outb(IRCR1_TMR_EN, iobase+IRCR1);
1510 switch_bank(iobase, BANK0);
1511 outb(IER_TMR_IE, iobase+IER);
1520 switch_bank(iobase, BANK0);
1521 outb(IER_DMA_IE, iobase+IER);
1524 nsc_ircc_dma_xmit(self, iobase);
1533 outb(bank, iobase+BSR);
1543 * Function nsc_ircc_dma_xmit (self, iobase)
1548 static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase)
1553 bsr = inb(iobase+BSR);
1556 switch_bank(iobase, BANK0);
1557 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1562 switch_bank(iobase, BANK2);
1563 outb(ECR1_DMASWP|ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
1572 switch_bank(iobase, BANK0);
1573 outb(inb(iobase+MCR)|MCR_TX_DFR|MCR_DMA_EN|MCR_IR_PLS, iobase+MCR);
1576 outb(bsr, iobase+BSR);
1580 * Function nsc_ircc_pio_xmit (self, iobase)
1586 static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
1594 bank = inb(iobase+BSR);
1596 switch_bank(iobase, BANK0);
1597 if (!(inb_p(iobase+LSR) & LSR_TXEMP)) {
1608 outb(buf[actual++], iobase+TXD);
1615 outb(bank, iobase+BSR);
1629 int iobase;
1635 iobase = self->io.fir_base;
1638 bank = inb(iobase+BSR);
1641 switch_bank(iobase, BANK0);
1642 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1645 if (inb(iobase+ASCR) & ASCR_TXUR) {
1650 outb(ASCR_TXUR, iobase+ASCR);
1661 nsc_ircc_dma_xmit(self, iobase);
1680 outb(bank, iobase+BSR);
1694 int iobase;
1697 iobase = self->io.fir_base;
1704 bsr = inb(iobase+BSR);
1707 switch_bank(iobase, BANK0);
1708 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1711 switch_bank(iobase, BANK2);
1712 outb(ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
1718 switch_bank(iobase, BANK0);
1719 outb(FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
1728 switch_bank(iobase, BANK0);
1729 outb(inb(iobase+MCR)|MCR_DMA_EN, iobase+MCR);
1732 outb(bsr, iobase+BSR);
1744 static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase)
1755 bank = inb(iobase+BSR);
1758 switch_bank(iobase, BANK5);
1759 while ((status = inb(iobase+FRM_ST)) & FRM_ST_VLD) {
1761 len = inb(iobase+RFLFL) | ((inb(iobase+RFLFH) & 0x1f) << 8);
1818 switch_bank(iobase, BANK0);
1819 if (inb(iobase+LSR) & LSR_RXDA) {
1831 switch_bank(iobase, BANK4);
1832 outb(0x02, iobase+TMRL); /* x 125 us */
1833 outb(0x00, iobase+TMRH);
1836 outb(IRCR1_TMR_EN, iobase+IRCR1);
1839 outb(bank, iobase+BSR);
1860 outb(bank, iobase+BSR);
1894 outb(bank, iobase+BSR);
1908 int iobase;
1910 iobase = self->io.fir_base;
1914 byte = inb(iobase+RXD);
1917 } while (inb(iobase+LSR) & LSR_RXDA); /* Data available */
1991 static void nsc_ircc_fir_interrupt(struct nsc_ircc_cb *self, int iobase,
1996 bank = inb(iobase+BSR);
2001 if (nsc_ircc_dma_receive_complete(self, iobase)) {
2009 switch_bank(iobase, BANK4);
2010 outb(0, iobase+IRCR1);
2013 switch_bank(iobase, BANK0);
2014 outb(ASCR_CTE, iobase+ASCR);
2018 nsc_ircc_dma_xmit(self, iobase);
2024 if (nsc_ircc_dma_receive_complete(self, iobase)) {
2063 outb(bank, iobase+BSR);
2077 int iobase;
2083 iobase = self->io.fir_base;
2085 bsr = inb(iobase+BSR); /* Save current bank */
2087 switch_bank(iobase, BANK0);
2088 self->ier = inb(iobase+IER);
2089 eir = inb(iobase+EIR) & self->ier; /* Mask out the interesting ones */
2091 outb(0, iobase+IER); /* Disable interrupts */
2096 nsc_ircc_fir_interrupt(self, iobase, eir);
2101 outb(self->ier, iobase+IER); /* Restore interrupts */
2102 outb(bsr, iobase+BSR); /* Restore bank register */
2118 int iobase;
2126 iobase = self->io.fir_base;
2129 bank = inb(iobase+BSR);
2130 switch_bank(iobase, BANK2);
2131 if ((inb(iobase+RXFLV) & 0x3f) != 0) {
2135 outb(bank, iobase+BSR);
2153 int iobase;
2164 iobase = self->io.fir_base;
2183 bank = inb(iobase+BSR);
2186 switch_bank(iobase, BANK0);
2187 outb(IER_LS_IE | IER_RXHDL_IE, iobase+IER);
2190 outb(bank, iobase+BSR);
2216 int iobase;
2234 iobase = self->io.fir_base;
2239 bank = inb(iobase+BSR);
2242 switch_bank(iobase, BANK0);
2243 outb(0, iobase+IER);
2249 outb(bank, iobase+BSR);
2314 int iobase = self->io.fir_base;
2326 bank = inb(iobase+BSR);
2329 switch_bank(iobase, BANK0);
2330 outb(0, iobase+IER);
2333 outb(bank, iobase+BSR);