Lines Matching refs:rval
164 __u16 rval;
167 ret = mcs_get_reg(mcs, MCS_XCVR_REG, &rval);
178 rval |= (MCS_MODE0 | MCS_XCVR_CONF);
179 rval &= ~MCS_STFIR;
180 rval &= ~MCS_MODE1;
181 ret = mcs_set_reg(mcs, MCS_XCVR_REG, rval);
185 rval &= ~MCS_MODE0;
186 ret = mcs_set_reg(mcs, MCS_XCVR_REG, rval);
190 rval &= ~MCS_XCVR_CONF;
191 ret = mcs_set_reg(mcs, MCS_XCVR_REG, rval);
218 __u16 rval;
226 ret = mcs_get_reg(mcs, MCS_MODE_REG, &rval);
229 rval |= MCS_DRIVER; /* put the mcs7780 into configuration mode. */
230 ret = mcs_set_reg(mcs, MCS_MODE_REG, rval);
234 rval = 0; /* set min pulse width to 0 initially. */
235 ret = mcs_set_reg(mcs, MCS_MINRXPW_REG, rval);
239 ret = mcs_get_reg(mcs, MCS_MODE_REG, &rval);
243 rval &= ~MCS_FIR; /* turn off fir mode. */
245 rval |= MCS_SIR16US; /* 1.6us pulse width */
247 rval &= ~MCS_SIR16US; /* 3/16 bit time pulse width */
250 rval &= ~(MCS_BBTG | MCS_ASK);
252 rval &= ~MCS_SPEED_MASK;
253 rval |= MCS_SPEED_9600; /* make sure initial speed is 9600. */
256 rval &= ~MCS_PLLPWDN; /* disable power down. */
261 rval |= MCS_DTD | MCS_SIPEN;
263 ret = mcs_set_reg(mcs, MCS_MODE_REG, rval);
294 ret = mcs_get_reg(mcs, MCS_XCVR_REG, &rval);
298 rval |= MCS_RXFAST;
300 rval &= ~MCS_RXFAST;
301 ret = mcs_set_reg(mcs, MCS_XCVR_REG, rval);
308 ret = mcs_get_reg(mcs, MCS_MODE_REG, &rval);
313 rval &= ~MCS_RESET;
314 ret = mcs_set_reg(mcs, MCS_MODE_REG, rval);
581 __u16 rval;
586 mcs_get_reg(mcs, MCS_RESV_REG, &rval);
587 } while(cnt++ < 100 && (rval & MCS_IRINTX));
595 mcs_get_reg(mcs, MCS_MODE_REG, &rval);
599 rval &= ~MCS_FIR;
605 rval &= ~MCS_FIR;
611 rval |= MCS_FIR;
618 rval &= ~MCS_SPEED_MASK;
619 rval |= nspeed;
621 ret = mcs_set_reg(mcs, MCS_MODE_REG, rval);
647 mcs_get_reg(mcs, MCS_MODE_REG, &rval);
648 rval &= ~MCS_RESET;
649 ret = mcs_set_reg(mcs, MCS_MODE_REG, rval);