Lines Matching refs:iobase
118 static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
135 static void SIR2FIR(int iobase);
136 static void FIR2SIR(int iobase);
314 IRDA_WARNING("%s(), can't get iobase of 0x%03x\n", __FUNCTION__,
415 int iobase;
421 iobase = self->io.fir_base;
552 int iobase = info->fir_base;
562 SIR2FIR(iobase);
565 outb(0x40, iobase+FIR_MCR); // benjamin 2000/11/30 11:45AM
568 switch_bank(iobase, BANK3);
569 version = inb(iobase+FIR_ID_VR);
580 switch_bank(iobase, BANK1);
581 outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
584 outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
587 switch_bank(iobase, BANK2);
588 outb(inb(iobase+FIR_IRDA_CR) | IRDA_CR_CRC, iobase+FIR_IRDA_CR);
593 switch_bank(iobase, BANK0);
595 tmp = inb(iobase+FIR_LCR_B);
599 outb(tmp, iobase+FIR_LCR_B);
602 outb(0x00, iobase+FIR_IER);
606 FIR2SIR(iobase);
612 // outb(UART_IER_RDI, iobase+UART_IER); //benjamin 2000/11/23 01:25PM
695 int iobase, tmp;
699 iobase = self->io.fir_base;
701 switch_bank(iobase, BANK0);
702 self->InterruptID = inb(iobase+FIR_IIR);
703 self->BusStatus = inb(iobase+FIR_BSR);
706 self->LineStatus = inb(iobase+FIR_LSR);
707 //self->ier = inb(iobase+FIR_IER); 2000/12/1 04:32PM
775 switch_bank(iobase, BANK1);
776 tmp = inb(iobase+FIR_CR);
777 outb( tmp& ~CR_TIMER_EN, iobase+FIR_CR);
816 int iobase;
821 iobase = self->io.sir_base;
823 iir = inb(iobase+UART_IIR) & UART_IIR_ID;
826 lsr = inb(iobase+UART_LSR);
828 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", __FUNCTION__,
829 iir, lsr, iobase);
870 int iobase;
875 iobase = self->io.sir_base;
883 inb(iobase+UART_RX));
890 } while (inb(iobase+UART_LSR) & UART_LSR_DR);
905 int iobase;
911 iobase = self->io.sir_base;
917 actual = ali_ircc_sir_write(iobase, self->io.fifo_size,
927 while(!(inb(iobase+UART_LSR) & UART_LSR_TEMT))
952 outb(UART_IER_RDI, iobase+UART_IER);
961 int iobase;
970 iobase = self->io.fir_base;
1010 int iobase;
1019 iobase = self->io.fir_base;
1026 SIR2FIR(iobase);
1048 int iobase;
1059 iobase = self->io.sir_base;
1067 FIR2SIR(iobase);
1072 inb(iobase+UART_LSR);
1073 inb(iobase+UART_SCR);
1097 outb(UART_LCR_DLAB | lcr, iobase+UART_LCR); /* Set DLAB */
1098 outb(divisor & 0xff, iobase+UART_DLL); /* Set speed */
1099 outb(divisor >> 8, iobase+UART_DLM);
1100 outb(lcr, iobase+UART_LCR); /* Set 8N1 */
1101 outb(fcr, iobase+UART_FCR); /* Enable FIFO's */
1105 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), iobase+UART_MCR);
1116 int iobase,dongle_id;
1121 iobase = self->io.fir_base; /* or iobase = self->io.sir_base; */
1128 switch_bank(iobase, BANK2);
1129 tmp = inb(iobase+FIR_IRDA_CR);
1145 switch_bank(iobase, BANK2);
1146 outb(tmp, iobase+FIR_IRDA_CR);
1151 outb(tmp, iobase+FIR_IRDA_CR);
1157 outb(tmp, iobase+FIR_IRDA_CR);
1162 outb(tmp, iobase+FIR_IRDA_CR);
1168 outb(tmp, iobase+FIR_IRDA_CR);
1174 outb(tmp, iobase+FIR_IRDA_CR);
1178 outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1201 switch_bank(iobase, BANK2);
1202 outb(tmp, iobase+FIR_IRDA_CR);
1206 //switch_bank(iobase, BANK2);
1210 outb(tmp, iobase+FIR_IRDA_CR);
1216 outb(tmp, iobase+FIR_IRDA_CR);
1221 outb(tmp, iobase+FIR_IRDA_CR);
1225 outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1248 switch_bank(iobase, BANK2);
1249 outb(tmp, iobase+FIR_IRDA_CR);
1258 switch_bank(iobase, BANK2);
1259 outb(tmp, iobase+FIR_IRDA_CR);
1283 switch_bank(iobase, BANK2);
1284 outb(tmp, iobase+FIR_IRDA_CR);
1288 switch_bank(iobase, BANK0);
1299 static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1306 if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) {
1314 outb(buf[actual], iobase+UART_TX);
1332 int iobase;
1343 iobase = self->io.fir_base;
1367 outb(UART_IER_RDI , iobase+UART_IER);
1396 //int iobase;
1436 int iobase;
1443 iobase = self->io.fir_base;
1521 switch_bank(iobase, BANK1);
1522 outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR);
1526 switch_bank(iobase, BANK1);
1527 outb(TIMER_IIR_1ms, iobase+FIR_TIMER_IIR);
1531 switch_bank(iobase, BANK1);
1532 outb(TIMER_IIR_2ms, iobase+FIR_TIMER_IIR);
1537 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1567 switch_bank(iobase, BANK0);
1580 int iobase, tmp;
1586 iobase = self->io.fir_base;
1596 switch_bank(iobase, BANK1);
1597 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1608 switch_bank(iobase, BANK0);
1609 outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1614 switch_bank(iobase, BANK1);
1615 outb(FIFO_OPTI, iobase+FIR_FIFO_TR) ;
1620 switch_bank(iobase, BANK1);
1621 outb(TX_DMA_Threshold, iobase+FIR_DMA_TR);
1626 switch_bank(iobase, BANK2);
1627 outb(Hi, iobase+FIR_TX_DSR_HI);
1628 outb(Lo, iobase+FIR_TX_DSR_LO);
1631 switch_bank(iobase, BANK0);
1632 tmp = inb(iobase+FIR_LCR_B);
1634 outb(((unsigned char)(tmp & 0x3f) | LCR_B_TX_MODE) & ~LCR_B_BW, iobase+FIR_LCR_B);
1635 IRDA_DEBUG(1, "%s(), ******* Change to TX mode: FIR_LCR_B = 0x%x ******* \n", __FUNCTION__ , inb(iobase+FIR_LCR_B));
1637 outb(0, iobase+FIR_LSR);
1640 switch_bank(iobase, BANK1);
1641 outb(inb(iobase+FIR_CR) | CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1643 switch_bank(iobase, BANK0);
1650 int iobase;
1655 iobase = self->io.fir_base;
1658 switch_bank(iobase, BANK1);
1659 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1662 switch_bank(iobase, BANK0);
1663 if((inb(iobase+FIR_LSR) & LSR_FRAME_ABORT) == LSR_FRAME_ABORT)
1707 switch_bank(iobase, BANK0);
1722 int iobase, tmp;
1726 iobase = self->io.fir_base;
1733 switch_bank(iobase, BANK1);
1734 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1737 switch_bank(iobase, BANK0);
1738 outb(0x07, iobase+FIR_LSR);
1742 self->LineStatus = inb(iobase+FIR_LSR) ;
1749 // switch_bank(iobase, BANK0);
1750 outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1759 //switch_bank(iobase, BANK0);
1760 tmp = inb(iobase+FIR_LCR_B);
1761 outb((unsigned char)(tmp &0x3f) | LCR_B_RX_MODE | LCR_B_BW , iobase + FIR_LCR_B); // 2000/12/1 05:16PM
1762 IRDA_DEBUG(1, "%s(), *** Change To RX mode: FIR_LCR_B = 0x%x *** \n", __FUNCTION__ , inb(iobase+FIR_LCR_B));
1765 switch_bank(iobase, BANK1);
1766 outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
1767 outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
1770 // switch_bank(iobase, BANK1);
1771 outb(CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1773 switch_bank(iobase, BANK0);
1783 int len, i, iobase, val;
1788 iobase = self->io.fir_base;
1790 switch_bank(iobase, BANK0);
1791 MessageCount = inb(iobase+ FIR_LSR)&0x07;
1799 switch_bank(iobase, BANK0);
1800 status = inb(iobase+FIR_LSR);
1802 switch_bank(iobase, BANK2);
1803 len = inb(iobase+FIR_RX_DSR_HI) & 0x0f;
1805 len |= inb(iobase+FIR_RX_DSR_LO);
1874 switch_bank(iobase, BANK0);
1875 val = inb(iobase+FIR_BSR);
1893 switch_bank(iobase, BANK1);
1894 outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR); // 2001/1/2 05:07PM
1897 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1941 switch_bank(iobase, BANK0);
1959 int iobase;
1969 iobase = self->io.sir_base;
2004 outb(UART_IER_THRI, iobase+UART_IER);
2085 int iobase;
2095 iobase = self->io.fir_base;
2097 switch_bank(iobase, BANK1);
2098 if((inb(iobase+FIR_FIFO_FR) & 0x3f) != 0)
2104 switch_bank(iobase, BANK0);
2168 int iobase = self->io.fir_base; /* or sir_base */
2205 switch_bank(iobase, BANK0);
2206 outb(newMask, iobase+FIR_IER);
2209 outb(newMask, iobase+UART_IER);
2214 static void SIR2FIR(int iobase)
2223 outb(0x28, iobase+UART_MCR);
2224 outb(0x68, iobase+UART_MCR);
2225 outb(0x88, iobase+UART_MCR);
2227 outb(0x60, iobase+FIR_MCR); /* Master Reset */
2228 outb(0x20, iobase+FIR_MCR); /* Master Interrupt Enable */
2230 //tmp = inb(iobase+FIR_LCR_B); /* SIP enable */
2232 //outb(tmp, iobase+FIR_LCR_B);
2237 static void FIR2SIR(int iobase)
2246 outb(0x20, iobase+FIR_MCR); /* IRQ to low */
2247 outb(0x00, iobase+UART_IER);
2249 outb(0xA0, iobase+FIR_MCR); /* Don't set master reset */
2250 outb(0x00, iobase+UART_FCR);
2251 outb(0x07, iobase+UART_FCR);
2253 val = inb(iobase+UART_RX);
2254 val = inb(iobase+UART_LSR);
2255 val = inb(iobase+UART_MSR);