Lines Matching refs:gp
69 //- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS);
70 //- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM);
71 //- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM | 1<<pcrLPBKBit);
103 static void read_mib_counters(struct gt64240_private *gp);
108 static void update_stats(struct gt64240_private *gp);
238 struct gt64240_private *gp = netdev_priv(dev);
241 spin_lock_irq(&gp->lock);
242 rc = mii_ethtool_gset(&gp->mii_if, cmd);
243 spin_unlock_irq(&gp->lock);
249 struct gt64240_private *gp = netdev_priv(dev);
252 spin_lock_irq(&gp->lock);
253 rc = mii_ethtool_sset(&gp->mii_if, cmd);
254 spin_unlock_irq(&gp->lock);
260 struct gt64240_private *gp = netdev_priv(dev);
261 return mii_nway_restart(&gp->mii_if);
266 struct gt64240_private *gp = netdev_priv(dev);
267 return mii_link_ok(&gp->mii_if);
272 struct gt64240_private *gp = netdev_priv(dev);
273 return gp->msg_enable;
278 struct gt64240_private *gp = netdev_priv(dev);
279 gp->msg_enable = value;
294 struct gt64240_private *gp = netdev_priv(dev);
302 spin_lock_irq(&gp->lock);
303 retval = generic_mii_ioctl(&gp->mii_if, data, cmd, NULL);
304 spin_unlock_irq(&gp->lock);
311 struct gt64240_private *gp = netdev_priv(dev);
312 gt64240_td_t *td = &gp->tx_ring[i];
321 struct gt64240_private *gp = netdev_priv(dev);
322 gt64240_rd_t *rd = &gp->rx_ring[i];
353 struct gt64240_private *gp = netdev_priv(dev);
357 if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
361 if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
380 struct gt64240_private *gp;
405 gp = netdev_priv(dev);
426 entry = (u32 *) ((u32) gp->hash_table +
449 static void read_mib_counters(struct gt64240_private *gp)
451 u32 *mib_regs = (u32 *) & gp->mib;
456 GT64240ETH_READ(gp,
462 static void update_stats(struct gt64240_private *gp)
464 mib_counters_t *mib = &gp->mib;
465 struct net_device_stats *stats = &gp->stats;
467 read_mib_counters(gp);
489 struct gt64240_private *gp = netdev_priv(dev);
502 spin_lock(&gp->lock);
505 GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, abort_bits);
509 dev->name, abort_bits, GT64240ETH_READ(gp,
513 while ((GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM)) & abort_bits) {
523 spin_unlock(&gp->lock);
529 struct gt64240_private *gp = netdev_priv(dev);
539 GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, 0);
542 dev->name, GT64240ETH_READ(gp,
549 struct gt64240_private *gp = netdev_priv(dev);
554 cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
555 - gp->tx_ring_dma) / sizeof(gt64240_td_t);
558 nextOut = gp->tx_next_out;
561 dev->name, GT64240ETH_READ(gp,
564 td = &gp->tx_ring[nextOut];
579 for (nextOut = gp->tx_next_out; nextOut != cdp;
582 if (--gp->intr_work_done == 0)
585 td = &gp->tx_ring[nextOut];
599 gp->stats.tx_errors++;
601 gp->stats.tx_aborted_errors++;
603 gp->stats.tx_fifo_errors++;
605 gp->stats.tx_window_errors++;
609 gp->stats.collisions +=
614 if (gp->tx_full) {
615 gp->tx_full = 0;
616 if (gp->last_psr & psrLink) {
621 if (gp->tx_count)
622 gp->tx_count--;
625 if (gp->tx_skbuff[nextOut]) {
629 dev->name, gp->tx_skbuff[nextOut]);
630 dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
631 gp->tx_skbuff[nextOut] = NULL;
637 gp->tx_next_out = nextOut;
639 if ((status & icrTxEndLow) && gp->tx_count != 0) {
641 GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
649 struct gt64240_private *gp = netdev_priv(dev);
657 spin_lock(&gp->lock);
662 gp->intr_work_done = max_interrupt_work;
664 while (gp->intr_work_done > 0) {
666 status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
670 GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
673 GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
678 gp->intr_work_done, status);
691 GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS);
692 if (gp->last_psr != psr) {
712 if ((psr & psrLink) && !gp->tx_full &&
726 gp->last_psr = psr;
753 if (gp->intr_work_done == 0) {
755 GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
762 dev->name, GT64240ETH_READ(gp,
765 spin_unlock(&gp->lock);
772 struct gt64240_private *gp = netdev_priv(dev);
782 //- GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0); /* CLEAR existing ints */
784 GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, intMask);
789 intMask |= 1 << gp->port_num;
795 struct gt64240_private *gp = netdev_priv(dev);
799 intMask &= ~(1 << gp->port_num);
803 GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, 0);
850 struct gt64240_private *gp = NULL;
886 gp = dev->priv;
888 gp->msg_enable = (debug < 0 ? GT64240_MSG_ENABLE : debug);
889 gp->port_num = port_num;
890 gp->io_size = GT64240_ETH_IO_SIZE;
891 gp->port_offset = port_num * GT64240_ETH_IO_SIZE;
892 gp->phy_addr = gt64240_phy_addr[port_num];
894 printk("%s: GT64240 ethernet port %d\n", dev->name, gp->port_num);
901 gp->mii_if.dev = dev;
902 gp->mii_if.phy_id = dev->base_addr;
903 gp->mii_if.mdio_read = read_MII;
904 gp->mii_if.mdio_write = write_MII;
905 gp->mii_if.advertising = read_MII(dev, gp->phy_addr, MII_ADVERTISE);
908 if (gp->rx_ring == NULL) {
910 gp->rx_ring = dma_alloc_noncoherent(NULL,
913 &gp->rx_ring_dma, GFP_KERNEL);
914 if (gp->rx_ring == NULL) {
919 gp->tx_ring = (gt64240_td_t *) (gp->rx_ring + RX_RING_SIZE);
920 gp->tx_ring_dma =
921 gp->rx_ring_dma + sizeof(gt64240_rd_t) * RX_RING_SIZE;
924 if (gp->rx_buff == NULL) {
925 gp->rx_buff = dma_alloc_coherent(NULL,
926 PKT_BUF_SZ * RX_RING_SIZE, &gp->rx_buff_dma,
928 if (gp->rx_buff == NULL) {
932 gp->rx_ring, gp->rx_ring_dma);
940 dev->name, gp->rx_ring, gp->tx_ring);
943 if (gp->hash_table == NULL) {
944 gp->hash_table = dma_alloc_coherent(NULL,
945 RX_HASH_TABLE_SIZE, &gp->hash_table_dma,
947 if (gp->hash_table == NULL) {
951 gp->rx_ring, gp->rx_ring_dma);
953 gp->rx_buff, gp->rx_buff_dma);
961 dev->name, gp->hash_table);
963 spin_lock_init(&gp->lock);
984 release_region(ioaddr, gp->io_size);
995 struct gt64240_private *gp = netdev_priv(dev);
1001 if (gp->tx_skbuff[i]) {
1003 dev_kfree_skb_irq(gp->tx_skbuff[i]);
1005 dev_kfree_skb(gp->tx_skbuff[i]);
1006 gp->tx_skbuff[i] = NULL;
1008 //- gp->tx_ring[i].cmdstat = 0; // CPU owns
1009 gp->tx_ring[i].cmdstat =
1011 gp->tx_ring[i].byte_cnt = 0;
1012 gp->tx_ring[i].buff_ptr = 0;
1013 gp->tx_ring[i].next =
1014 gp->tx_ring_dma + sizeof(gt64240_td_t) * (i + 1);
1019 gp->tx_ring[i - 1].next = gp->tx_ring_dma;
1024 GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
1025 gp->tx_ring_dma);
1026 //- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0, 0); /* ROLLINS */
1027 //- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,virt_to_phys(&gp->tx_ring[0])); /* ROLLINS */
1029 GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR1, 0);
1032 gp->tx_next_in = gp->tx_next_out = 0;
1033 gp->tx_count = 0;
1038 struct gt64240_private *gp = netdev_priv(dev);
1044 gp->rx_ring[i].next =
1045 gp->rx_ring_dma + sizeof(gt64240_rd_t) * (i + 1);
1046 gp->rx_ring[i].buff_ptr = gp->rx_buff_dma + i * PKT_BUF_SZ;
1047 gp->rx_ring[i].buff_sz = PKT_BUF_SZ;
1048 gp->rx_ring[i].byte_cnt = 0; /* just for debug printk's */
1050 gp->rx_ring[i].cmdstat =
1056 gp->rx_ring[i - 1].next = gp->rx_ring_dma;
1063 GT64240ETH_WRITE(gp, GT64240_ETH_1ST_RX_DESC_PTR0,
1064 gp->rx_ring_dma);
1065 GT64240ETH_WRITE(gp, GT64240_ETH_CURR_RX_DESC_PTR0,
1066 gp->rx_ring_dma);
1068 GT64240ETH_WRITE(gp,
1071 GT64240ETH_WRITE(gp,
1078 gp->rx_next_out = 0;
1084 struct gt64240_private *gp = netdev_priv(dev);
1113 memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it
1114 gp->hash_mode = 0;
1118 GT64240ETH_WRITE(gp, GT64240_ETH_HASH_TBL_PTR, gp->hash_table_dma);
1121 GT64240ETH_READ(gp, GT64240_ETH_HASH_TBL_PTR));
1128 dev->name, GT64240ETH_READ(gp,
1136 dev->name, GT64240ETH_READ(gp,
1138 GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0));
1144 write_MII(dev, gp->phy_addr, 0, 0x8000);
1154 GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG,
1158 GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG, sdcrBLMR | sdcrBLMT |
1166 GT64240ETH_READ(gp, GT64240_ETH_SDMA_CONFIG));
1171 GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM));
1173 GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, PORT_CONFIG);
1177 GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
1188 GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
1190 read_mib_counters(gp);
1191 GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
1196 GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG_EXT));
1200 GT64240ETH_READ(gp, GT64240_ETH_PORT_COMMAND));
1201 GT64240ETH_WRITE(gp, GT64240_ETH_PORT_COMMAND, 0x0);
1206 GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
1210 GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
1212 GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
1218 //--- gp->last_psr |= psrLink; /* KLUDGE ALERT */
1275 struct gt64240_private *gp = netdev_priv(dev);
1280 cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
1281 - gp->tx_ring_dma) / sizeof(gt64240_td_t);
1283 for (nextOut = gp->tx_next_out; nextOut != cdp;
1285 if (--gp->intr_work_done == 0)
1288 td = &gp->tx_ring[nextOut];
1294 if (gp->tx_full) {
1295 gp->tx_full = 0;
1296 if (gp->last_psr & psrLink) {
1301 if (gp->tx_count)
1302 gp->tx_count--;
1305 if (gp->tx_skbuff[nextOut]) {
1306 dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
1307 gp->tx_skbuff[nextOut] = NULL;
1311 gp->tx_next_out = nextOut;
1313 if ((status & icrTxEndLow) && gp->tx_count != 0)
1315 GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
1324 struct gt64240_private *gp = netdev_priv(dev);
1327 u32 status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
1329 spin_lock_irqsave(&gp->lock, flags);
1332 if (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0) !=
1333 gp->rx_next_out) {
1349 spin_unlock_irqrestore(&gp->lock, flags);
1357 struct gt64240_private *gp = netdev_priv(dev);
1361 spin_lock_irqsave(&gp->lock, flags);
1363 nextIn = gp->tx_next_in;
1369 if (gp->tx_count >= TX_RING_SIZE) {
1371 gp->stats.tx_dropped++;
1372 spin_unlock_irqrestore(&gp->lock, flags);
1376 if (!(gp->last_psr & psrLink)) {
1379 gp->stats.tx_dropped++;
1380 spin_unlock_irqrestore(&gp->lock, flags);
1385 if (gp->tx_ring[nextIn].cmdstat & txOwn) {
1389 gp->stats.tx_dropped++;
1392 spin_unlock_irqrestore(&gp->lock, flags);
1396 gp->tx_skbuff[nextIn] = skb;
1397 gp->tx_ring[nextIn].byte_cnt = skb->len;
1398 gp->tx_ring[nextIn].buff_ptr = virt_to_phys(skb->data);
1406 gp->tx_ring[nextIn].cmdstat =
1413 gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE;
1417 GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
1418 virt_to_phys(&gp->tx_ring[nextIn]));
1424 dev->name, GT64240ETH_READ(gp,
1426 GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
1429 if (!((GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS)) & psrTxLow)) {
1430 GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
1437 dev->name, GT64240ETH_READ(gp,
1439 GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
1442 if (++gp->tx_count >= TX_RING_SIZE) {
1443 gp->tx_full = 1;
1448 spin_unlock_irqrestore(&gp->lock, flags);
1461 struct gt64240_private *gp = netdev_priv(dev);
1471 cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0)
1472 - gp->rx_ring_dma) / sizeof(gt64240_rd_t);
1475 for (nextOut = gp->rx_next_out; nextOut != cdp;
1485 if (--gp->intr_work_done == 0)
1491 rd = &gp->rx_ring[nextOut];
1523 gp->stats.rx_fifo_errors++;
1537 gp->stats.rx_dropped++;
1545 &gp->rx_buff[nextOut * PKT_BUF_SZ], pkt_len);
1563 if (gt64240_debug > 3 && nextOut == gp->rx_next_out)
1567 gp->rx_next_out = nextOut;
1574 struct gt64240_private *gp = netdev_priv(dev);
1577 spin_lock_irqsave(&gp->lock, flags);
1580 if (!(gp->last_psr & psrLink)) {
1581 spin_unlock_irqrestore(&gp->lock, flags);
1587 spin_unlock_irqrestore(&gp->lock, flags);
1598 struct gt64240_private *gp = netdev_priv(dev);
1609 spin_lock_irqsave(&gp->lock, flags);
1612 GT64240ETH_SETBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
1614 GT64240ETH_CLRBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
1616 GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
1620 memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear hash table
1636 GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
1639 GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
1641 spin_unlock_irqrestore(&gp->lock, flags);
1646 struct gt64240_private *gp = netdev_priv(dev);
1653 spin_lock_irqsave(&gp->lock, flags);
1654 update_stats(gp);
1655 spin_unlock_irqrestore(&gp->lock, flags);
1658 return &gp->stats;