Lines Matching refs:irqmask
738 u32 irqmask;
981 /* In MSIX mode, a write to irqmask behaves as XOR */
2839 if (!(events & np->irqmask))
2852 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2857 writel(np->irqmask, base + NvRegIrqMask);
2895 writel(np->irqmask, base + NvRegIrqMask);
2899 np->nic_poll_irq = np->irqmask;
2912 writel(np->irqmask, base + NvRegIrqMask);
2916 np->nic_poll_irq = np->irqmask;
2956 if (!(events & np->irqmask))
2969 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2974 writel(np->irqmask, base + NvRegIrqMask);
3012 writel(np->irqmask, base + NvRegIrqMask);
3016 np->nic_poll_irq = np->irqmask;
3030 writel(np->irqmask, base + NvRegIrqMask);
3034 np->nic_poll_irq = np->irqmask;
3063 if (!(events & np->irqmask))
3126 np->irqmask |= NVREG_IRQ_RX_ALL;
3130 writel(np->irqmask, base + NvRegIrqMask);
3177 if (!(events & np->irqmask))
3225 if (!(events & np->irqmask))
3313 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3324 if ((irqmask >> i) & 0x1) {
3332 if ((irqmask >> (i + 8)) & 0x1) {
3475 mask = np->irqmask;
4473 nv_disable_hw_interrupts(dev, np->irqmask);
4530 nv_enable_hw_interrupts(dev, np->irqmask);
4727 nv_disable_hw_interrupts(dev, np->irqmask);
4738 nv_enable_hw_interrupts(dev, np->irqmask);
4808 nv_disable_hw_interrupts(dev, np->irqmask);
5094 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5098 np->irqmask = NVREG_IRQMASK_CPU;
5104 np->irqmask |= NVREG_IRQ_TIMER;