Lines Matching refs:np
473 struct netdev_private *np;
543 np = netdev_priv(dev);
544 np->mem = ioaddr;
545 spin_lock_init(&np->lock);
546 np->pci_dev = pdev;
547 np->flags = skel_netdrv_tbl[chip_id].flags;
549 np->mii.dev = dev;
550 np->mii.mdio_read = mdio_read;
551 np->mii.mdio_write = mdio_write;
552 np->mii.phy_id_mask = 0x1f;
553 np->mii.reg_num_mask = 0x1f;
560 np->rx_ring = (struct fealnx_desc *)ring_space;
561 np->rx_ring_dma = ring_dma;
568 np->tx_ring = (struct fealnx_desc *)ring_space;
569 np->tx_ring_dma = ring_dma;
572 if (np->flags == HAS_MII_XCVR) {
579 np->phys[phy_idx++] = phy;
587 data = mdio_read(dev, np->phys[0], 2);
589 np->PHYType = SeeqPHY;
591 np->PHYType = AhdocPHY;
593 np->PHYType = MarvellPHY;
595 np->PHYType = Myson981;
597 np->PHYType = LevelOnePHY;
599 np->PHYType = OtherPHY;
604 np->mii_cnt = phy_idx;
610 np->phys[0] = 32;
614 np->PHYType = MysonPHY;
616 np->PHYType = OtherPHY;
618 np->mii.phy_id = np->phys[0];
626 np->mii.full_duplex = 1;
627 np->default_port = option & 15;
631 np->mii.full_duplex = full_duplex[card_idx];
633 if (np->mii.full_duplex) {
636 // if (np->PHYType==MarvellPHY)
637 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
640 data = mdio_read(dev, np->phys[0], 9);
642 mdio_write(dev, np->phys[0], 9, data);
645 if (np->flags == HAS_MII_XCVR)
646 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
649 np->mii.force_media = 1;
676 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
678 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
694 struct netdev_private *np = netdev_priv(dev);
696 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
697 np->tx_ring_dma);
698 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
699 np->rx_ring_dma);
701 pci_iounmap(pdev, np->mem);
761 struct netdev_private *np = netdev_priv(dev);
762 void __iomem *miiport = np->mem + MANAGEMENT;
800 struct netdev_private *np = netdev_priv(dev);
801 void __iomem *miiport = np->mem + MANAGEMENT;
832 struct netdev_private *np = netdev_priv(dev);
833 void __iomem *ioaddr = np->mem;
847 iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
848 iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
853 // np->bcrvalue=0x04 | 0x0x38; /* big-endian, 256 burst length */
854 np->bcrvalue = 0x04 | 0x10; /* big-endian, tx 8 burst length */
855 np->crvalue = 0xe00; /* rx 128 burst length */
858 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
859 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
860 np->crvalue = 0xe00; /* rx 128 burst length */
864 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
865 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
866 np->crvalue = 0xe00; /* rx 128 burst length */
870 // np->bcrvalue=(x86 <= 4 ? 0x10 : 0x38);
871 np->bcrvalue = 0x10;
872 np->crvalue = (x86 <= 4 ? 0xa00 : 0xe00);
879 // np->bcrvalue=0x38;
880 np->bcrvalue = 0x10;
881 np->crvalue = 0xe00; /* rx 128 burst length */
886 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
887 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
888 if (np->pci_dev->device == 0x891) {
889 np->bcrvalue |= 0x200; /* set PROG bit */
890 np->crvalue |= CR_W_ENH; /* set enhanced bit */
891 np->imrvalue |= ETI;
893 iowrite32(np->bcrvalue, ioaddr + BCR);
896 dev->if_port = np->default_port;
900 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
901 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
902 np->mii.full_duplex = np->mii.force_media;
904 if (np->linkok)
912 iowrite32(np->imrvalue, ioaddr + IMR);
918 init_timer(&np->timer);
919 np->timer.expires = RUN_AT(3 * HZ);
920 np->timer.data = (unsigned long) dev;
921 np->timer.function = &netdev_timer;
924 add_timer(&np->timer);
926 init_timer(&np->reset_timer);
927 np->reset_timer.data = (unsigned long) dev;
928 np->reset_timer.function = &reset_timer;
929 np->reset_timer_armed = 0;
940 struct netdev_private *np = netdev_priv(dev);
943 np->linkok = 0;
945 if (np->PHYType == MysonPHY) {
947 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
948 np->linkok = 1;
955 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
956 np->linkok = 1;
967 struct netdev_private *np = netdev_priv(dev);
969 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
970 if (ioread32(np->mem + TCRRCR) & CR_R_FD)
971 np->duplexmode = 2; /* full duplex */
973 np->duplexmode = 1; /* half duplex */
974 if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
975 np->line_speed = 1; /* 10M */
977 np->line_speed = 2; /* 100M */
979 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
982 data = mdio_read(dev, np->phys[0], MIIRegister18);
984 np->line_speed = 2; /* 100M */
986 np->line_speed = 1; /* 10M */
988 np->duplexmode = 2; /* full duplex mode */
990 np->duplexmode = 1; /* half duplex mode */
991 } else if (np->PHYType == AhdocPHY) {
994 data = mdio_read(dev, np->phys[0], DiagnosticReg);
996 np->line_speed = 2; /* 100M */
998 np->line_speed = 1; /* 10M */
1000 np->duplexmode = 2; /* full duplex mode */
1002 np->duplexmode = 1; /* half duplex mode */
1005 else if (np->PHYType == MarvellPHY) {
1008 data = mdio_read(dev, np->phys[0], SpecificReg);
1010 np->duplexmode = 2; /* full duplex mode */
1012 np->duplexmode = 1; /* half duplex mode */
1015 np->line_speed = 3; /* 1000M */
1017 np->line_speed = 2; /* 100M */
1019 np->line_speed = 1; /* 10M */
1023 else if (np->PHYType == Myson981) {
1026 data = mdio_read(dev, np->phys[0], StatusRegister);
1029 np->line_speed = 2;
1031 np->line_speed = 1;
1034 np->duplexmode = 2;
1036 np->duplexmode = 1;
1040 else if (np->PHYType == LevelOnePHY) {
1043 data = mdio_read(dev, np->phys[0], SpecificReg);
1045 np->duplexmode = 2; /* full duplex mode */
1047 np->duplexmode = 1; /* half duplex mode */
1050 np->line_speed = 3; /* 1000M */
1052 np->line_speed = 2; /* 100M */
1054 np->line_speed = 1; /* 10M */
1056 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1057 if (np->line_speed == 1)
1058 np->crvalue |= CR_W_PS10;
1059 else if (np->line_speed == 3)
1060 np->crvalue |= CR_W_PS1000;
1061 if (np->duplexmode == 2)
1062 np->crvalue |= CR_W_FD;
1070 struct netdev_private *np = netdev_priv(dev);
1073 while (np->really_rx_count != RX_RING_SIZE) {
1076 skb = dev_alloc_skb(np->rx_buf_sz);
1080 while (np->lack_rxbuf->skbuff)
1081 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1084 np->lack_rxbuf->skbuff = skb;
1085 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1086 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1087 np->lack_rxbuf->status = RXOWN;
1088 ++np->really_rx_count;
1096 struct netdev_private *np = netdev_priv(dev);
1097 void __iomem *ioaddr = np->mem;
1098 int old_crvalue = np->crvalue;
1099 unsigned int old_linkok = np->linkok;
1107 spin_lock_irqsave(&np->lock, flags);
1109 if (np->flags == HAS_MII_XCVR) {
1111 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1113 if (np->crvalue != old_crvalue) {
1114 stop_nic_rxtx(ioaddr, np->crvalue);
1115 iowrite32(np->crvalue, ioaddr + TCRRCR);
1122 spin_unlock_irqrestore(&np->lock, flags);
1124 np->timer.expires = RUN_AT(10 * HZ);
1125 add_timer(&np->timer);
1133 struct netdev_private *np = netdev_priv(dev);
1134 void __iomem *ioaddr = np->mem;
1159 struct netdev_private *np = netdev_priv(dev);
1160 void __iomem *ioaddr = np->mem;
1164 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1166 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1169 iowrite32(np->bcrvalue, ioaddr + BCR);
1172 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1176 iowrite32(np->imrvalue, ioaddr + IMR);
1185 struct netdev_private *np = netdev_priv(dev);
1190 spin_lock_irqsave(&np->lock, flags);
1191 np->crvalue = np->crvalue_sv;
1192 np->imrvalue = np->imrvalue_sv;
1200 np->reset_timer_armed = 0;
1202 spin_unlock_irqrestore(&np->lock, flags);
1208 struct netdev_private *np = netdev_priv(dev);
1209 void __iomem *ioaddr = np->mem;
1217 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1219 printk(" %8.8x", (unsigned int) np->rx_ring[i].status);
1220 printk("\n" KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1222 printk(" %4.4x", np->tx_ring[i].status);
1226 spin_lock_irqsave(&np->lock, flags);
1232 spin_unlock_irqrestore(&np->lock, flags);
1235 np->stats.tx_errors++;
1243 struct netdev_private *np = netdev_priv(dev);
1247 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1248 np->cur_rx = &np->rx_ring[0];
1249 np->lack_rxbuf = np->rx_ring;
1250 np->really_rx_count = 0;
1254 np->rx_ring[i].status = 0;
1255 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1256 np->rx_ring[i].next_desc = np->rx_ring_dma +
1258 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1259 np->rx_ring[i].skbuff = NULL;
1263 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1264 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1268 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1271 np->lack_rxbuf = &np->rx_ring[i];
1275 ++np->really_rx_count;
1276 np->rx_ring[i].skbuff = skb;
1278 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1279 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1280 np->rx_ring[i].status = RXOWN;
1281 np->rx_ring[i].control |= RXIC;
1285 np->cur_tx = &np->tx_ring[0];
1286 np->cur_tx_copy = &np->tx_ring[0];
1287 np->really_tx_count = 0;
1288 np->free_tx_count = TX_RING_SIZE;
1291 np->tx_ring[i].status = 0;
1292 np->tx_ring[i].next_desc = np->tx_ring_dma +
1294 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1295 np->tx_ring[i].skbuff = NULL;
1299 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1300 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1306 struct netdev_private *np = netdev_priv(dev);
1309 spin_lock_irqsave(&np->lock, flags);
1311 np->cur_tx_copy->skbuff = skb;
1316 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1318 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1319 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1320 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1322 if (np->pci_dev->device == 0x891)
1323 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1324 np->cur_tx_copy->status = TXOWN;
1325 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1326 --np->free_tx_count;
1332 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1334 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1335 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1336 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1339 next = np->cur_tx_copy->next_desc_logical;
1345 if (np->pci_dev->device == 0x891)
1346 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1351 np->cur_tx_copy->status = TXOWN;
1353 np->cur_tx_copy = next->next_desc_logical;
1354 np->free_tx_count -= 2;
1356 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1358 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1359 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1360 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1362 if (np->pci_dev->device == 0x891)
1363 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1364 np->cur_tx_copy->status = TXOWN;
1365 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1366 --np->free_tx_count;
1370 if (np->free_tx_count < 2)
1372 ++np->really_tx_count;
1373 iowrite32(0, np->mem + TXPDR);
1376 spin_unlock_irqrestore(&np->lock, flags);
1385 struct netdev_private *np = netdev_priv(dev);
1390 np->cur_tx = &np->tx_ring[0];
1391 np->cur_tx_copy = &np->tx_ring[0];
1392 np->really_tx_count = 0;
1393 np->free_tx_count = TX_RING_SIZE;
1396 cur = &np->tx_ring[i];
1398 pci_unmap_single(np->pci_dev, cur->buffer,
1406 cur->next_desc = np->tx_ring_dma +
1408 cur->next_desc_logical = &np->tx_ring[i + 1];
1411 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1412 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1419 struct netdev_private *np = netdev_priv(dev);
1420 struct fealnx_desc *cur = np->cur_rx;
1431 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1432 np->mem + RXLBA);
1441 struct netdev_private *np = netdev_priv(dev);
1442 void __iomem *ioaddr = np->mem;
1447 spin_lock(&np->lock);
1461 if (!(intr_status & np->imrvalue))
1480 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1483 np->stats.rx_crc_errors +=
1491 stop_nic_rx(ioaddr, np->crvalue);
1493 iowrite32(np->crvalue, ioaddr + TCRRCR);
1497 while (np->really_tx_count) {
1498 long tx_status = np->cur_tx->status;
1499 long tx_control = np->cur_tx->control;
1504 next = np->cur_tx->next_desc_logical;
1512 if (!(np->crvalue & CR_W_ENH)) {
1514 np->stats.tx_errors++;
1516 np->stats.tx_aborted_errors++;
1518 np->stats.tx_carrier_errors++;
1520 np->stats.tx_window_errors++;
1522 np->stats.tx_fifo_errors++;
1523 if ((tx_status & HF) && np->mii.full_duplex == 0)
1524 np->stats.tx_heartbeat_errors++;
1527 np->stats.tx_bytes +=
1530 np->stats.collisions +=
1532 np->stats.tx_packets++;
1535 np->stats.tx_bytes +=
1537 np->stats.tx_packets++;
1541 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1542 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1543 dev_kfree_skb_irq(np->cur_tx->skbuff);
1544 np->cur_tx->skbuff = NULL;
1545 --np->really_tx_count;
1546 if (np->cur_tx->control & TXLD) {
1547 np->cur_tx = np->cur_tx->next_desc_logical;
1548 ++np->free_tx_count;
1550 np->cur_tx = np->cur_tx->next_desc_logical;
1551 np->cur_tx = np->cur_tx->next_desc_logical;
1552 np->free_tx_count += 2;
1557 if (num_tx && np->free_tx_count >= 2)
1561 if (np->crvalue & CR_W_ENH) {
1565 np->stats.tx_errors += (data & 0xff000000) >> 24;
1566 np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
1567 np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
1568 np->stats.collisions += (data & 0x0000ffff);
1574 if (!np->reset_timer_armed) {
1575 np->reset_timer_armed = 1;
1576 np->reset_timer.expires = RUN_AT(HZ/2);
1577 add_timer(&np->reset_timer);
1582 np->crvalue_sv = np->crvalue;
1583 np->imrvalue_sv = np->imrvalue;
1584 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1585 np->imrvalue = 0;
1594 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1597 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1603 iowrite32(np->imrvalue, ioaddr + IMR);
1605 spin_unlock(&np->lock);
1615 struct netdev_private *np = netdev_priv(dev);
1616 void __iomem *ioaddr = np->mem;
1619 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1620 s32 rx_status = np->cur_rx->status;
1622 if (np->really_rx_count == 0)
1636 np->stats.rx_errors++; /* end of a packet. */
1638 np->stats.rx_length_errors++;
1640 np->stats.rx_frame_errors++;
1642 np->stats.rx_crc_errors++;
1651 cur = np->cur_rx;
1652 while (desno <= np->really_rx_count) {
1660 if (desno > np->really_rx_count)
1668 np->stats.rx_length_errors++;
1672 if (!np->cur_rx->skbuff) {
1677 np->cur_rx->status = RXOWN;
1678 np->cur_rx = np->cur_rx->next_desc_logical;
1682 stop_nic_rx(ioaddr, np->crvalue);
1684 iowrite32(np->crvalue, ioaddr + TCRRCR);
1705 pci_dma_sync_single_for_cpu(np->pci_dev,
1706 np->cur_rx->buffer,
1707 np->rx_buf_sz,
1713 np->cur_rx->skbuff->data, pkt_len, 0);
1717 np->cur_rx->skbuff->data, pkt_len);
1719 pci_dma_sync_single_for_device(np->pci_dev,
1720 np->cur_rx->buffer,
1721 np->rx_buf_sz,
1724 pci_unmap_single(np->pci_dev,
1725 np->cur_rx->buffer,
1726 np->rx_buf_sz,
1728 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1729 np->cur_rx->skbuff = NULL;
1730 --np->really_rx_count;
1735 np->stats.rx_packets++;
1736 np->stats.rx_bytes += pkt_len;
1739 np->cur_rx = np->cur_rx->next_desc_logical;
1751 struct netdev_private *np = netdev_priv(dev);
1752 void __iomem *ioaddr = np->mem;
1756 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1757 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1760 return &np->stats;
1778 struct netdev_private *np = netdev_priv(dev);
1779 void __iomem *ioaddr = np->mem;
1805 stop_nic_rxtx(ioaddr, np->crvalue);
1809 np->crvalue &= ~CR_W_RXMODEMASK;
1810 np->crvalue |= rx_mode;
1811 iowrite32(np->crvalue, ioaddr + TCRRCR);
1816 struct netdev_private *np = netdev_priv(dev);
1820 strcpy(info->bus_info, pci_name(np->pci_dev));
1825 struct netdev_private *np = netdev_priv(dev);
1828 spin_lock_irq(&np->lock);
1829 rc = mii_ethtool_gset(&np->mii, cmd);
1830 spin_unlock_irq(&np->lock);
1837 struct netdev_private *np = netdev_priv(dev);
1840 spin_lock_irq(&np->lock);
1841 rc = mii_ethtool_sset(&np->mii, cmd);
1842 spin_unlock_irq(&np->lock);
1849 struct netdev_private *np = netdev_priv(dev);
1850 return mii_nway_restart(&np->mii);
1855 struct netdev_private *np = netdev_priv(dev);
1856 return mii_link_ok(&np->mii);
1883 struct netdev_private *np = netdev_priv(dev);
1889 spin_lock_irq(&np->lock);
1890 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1891 spin_unlock_irq(&np->lock);
1899 struct netdev_private *np = netdev_priv(dev);
1900 void __iomem *ioaddr = np->mem;
1911 del_timer_sync(&np->timer);
1912 del_timer_sync(&np->reset_timer);
1918 struct sk_buff *skb = np->rx_ring[i].skbuff;
1920 np->rx_ring[i].status = 0;
1922 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1923 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1925 np->rx_ring[i].skbuff = NULL;
1930 struct sk_buff *skb = np->tx_ring[i].skbuff;
1933 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1936 np->tx_ring[i].skbuff = NULL;