Lines Matching defs:GG82563_REG
2643 #define GG82563_REG(page, reg) \
2649 GG82563_REG(0, 16) /* PHY Specific Control */
2651 GG82563_REG(0, 17) /* PHY Specific Status */
2653 GG82563_REG(0, 18) /* Interrupt Enable */
2655 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2657 GG82563_REG(0, 21) /* Receive Error Counter */
2659 GG82563_REG(0, 22) /* Page Select */
2661 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2663 GG82563_REG(0, 29) /* Alternate Page Select */
2665 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2668 GG82563_REG(2, 21) /* MAC Specific Control Register */
2670 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2673 GG82563_REG(5, 26) /* DSP Distance */
2677 GG82563_REG(193, 16) /* Kumeran Mode Control */
2679 GG82563_REG(193, 17) /* Port Reset */
2681 GG82563_REG(193, 18) /* Revision ID */
2683 GG82563_REG(193, 19) /* Device ID */
2685 GG82563_REG(193, 20) /* Power Management Control */
2687 GG82563_REG(193, 25) /* Rate Adaptation Control */
2691 GG82563_REG(194, 16) /* FIFO's Control/Status */
2693 GG82563_REG(194, 17) /* Control */
2695 GG82563_REG(194, 18) /* Inband Control */
2697 GG82563_REG(194, 19) /* Diagnostic */
2699 GG82563_REG(194, 20) /* Acknowledge Timeouts */
2701 GG82563_REG(194, 21) /* Advertised Ability */
2703 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2705 GG82563_REG(194, 24) /* Advertised Next Page */
2707 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2709 GG82563_REG(194, 26) /* Misc. */