Lines Matching refs:x2
21 #define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
22 #define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
23 #define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
49 /*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */
50 /*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */
70 #define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */
71 #define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */
72 #define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */
73 #define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */
74 #define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */
75 #define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */
76 #define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */
77 #define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */
78 #define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */
79 #define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */
86 #define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4))
87 #define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b)
89 #define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */
90 #define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */
91 #define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */
92 #define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */
93 #define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */
94 #define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */
95 #define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */
96 #define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */
98 #define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */
99 #define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */
100 #define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */
101 #define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */
102 #define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */
103 #define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */
104 #define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */
285 #define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)
286 #define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
287 #define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d)
288 #define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d)
289 #define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)
290 #define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)
291 #define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)
292 #define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)