Lines Matching refs:hw_addr
272 iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
626 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
722 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
733 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
744 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
777 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
799 rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
808 iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
811 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
812 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
856 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
979 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
989 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
997 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1006 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1009 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1018 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1033 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1040 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1042 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1048 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1051 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1053 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1055 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1057 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1059 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1065 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1066 iowrite32(adapter->tpd_ring.count, hw->hw_addr + REG_DESC_TPD_RING_SIZE);
1069 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1078 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1089 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1099 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1102 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1103 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1106 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1109 iowrite32(hw->max_frame_size + 4, hw->hw_addr + REG_MTU);
1118 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1140 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1147 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1157 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1168 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1172 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1174 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1175 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1179 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1181 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1188 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1189 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1200 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
1201 ioread32(adapter->hw.hw_addr + REG_IMR);
1218 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
1220 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
1223 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
1225 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
1481 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1759 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2059 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
2061 value = ioread32(adapter->hw.hw_addr + 0x1008);
2063 iowrite32(value, adapter->hw.hw_addr + 0x1008);
2076 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
2079 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
2141 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2142 if (!adapter->hw.hw_addr) {
2147 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
2204 iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE);
2262 pci_iounmap(pdev, adapter->hw.hw_addr);
2301 iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE);
2303 pci_iounmap(pdev, adapter->hw.hw_addr);
2343 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2346 ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL);
2362 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2366 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2392 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);