Lines Matching refs:hw
36 * hw - Struct containing variables accessed by shared code
39 s32 atl1_reset_hw(struct atl1_hw *hw)
41 struct pci_dev *pdev = hw->back->pdev;
50 * iowrite32(0, hw->hw_addr + REG_IMR);
51 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
60 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
61 ioread32(hw->hw_addr + REG_MASTER_CTRL);
63 iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
64 ioread16(hw->hw_addr + REG_GPHY_ENABLE);
70 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
90 static int atl1_check_eeprom_exist(struct atl1_hw *hw)
93 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
96 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
99 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
103 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
111 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
113 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
114 ioread32(hw->hw_addr + REG_VPD_CAP);
118 control = ioread32(hw->hw_addr + REG_VPD_CAP);
123 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
131 * hw - Struct containing variables accessed by shared code
134 s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
142 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
143 ioread32(hw->hw_addr + REG_MDIO_CTRL);
147 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
164 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
169 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
170 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
185 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
188 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
189 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
193 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
201 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
210 static int atl1_get_permanent_address(struct atl1_hw *hw)
218 if (is_valid_ether_addr(hw->perm_mac_addr))
224 if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
230 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
250 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
262 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
282 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
292 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
293 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
297 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
306 * hw - Struct containing variables accessed by shared code
308 s32 atl1_read_mac_addr(struct atl1_hw *hw)
312 if (atl1_get_permanent_address(hw))
313 random_ether_addr(hw->perm_mac_addr);
316 hw->mac_addr[i] = hw->perm_mac_addr[i];
322 * hw - Struct containing variables accessed by shared code
332 u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
346 * hw - Struct containing variables accessed by shared code
349 void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
365 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
367 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
372 * hw - Struct containing variables accessed by shared code
376 s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
385 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
386 ioread32(hw->hw_addr + REG_MDIO_CTRL);
390 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
403 * hw - Struct containing variables accessed by shared code
407 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
410 ret = atl1_write_phy_reg(hw, 29, 0x0029);
413 return atl1_write_phy_reg(hw, 30, 0);
419 s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
426 ret_val = atl1_write_phy_reg(hw, ...);
427 ret_val = atl1_write_phy_reg(hw, ...);
435 * hw - Struct containing variables accessed by shared code
439 static s32 atl1_phy_reset(struct atl1_hw *hw)
441 struct pci_dev *pdev = hw->back->pdev;
445 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
446 hw->media_type == MEDIA_TYPE_1000M_FULL)
449 switch (hw->media_type) {
468 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
477 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
492 * hw - Struct containing variables accessed by shared code
494 s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
518 switch (hw->media_type) {
551 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
552 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
554 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
558 ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
567 * hw - Struct containing variables accessed by shared code
571 static s32 atl1_setup_link(struct atl1_hw *hw)
573 struct pci_dev *pdev = hw->back->pdev;
582 ret_val = atl1_phy_setup_autoneg_adv(hw);
588 ret_val = atl1_phy_reset(hw);
593 hw->phy_configured = true;
604 static void atl1_init_flash_opcode(struct atl1_hw *hw)
606 if (hw->flash_vendor >= sizeof(flash_table) / sizeof(flash_table[0]))
607 hw->flash_vendor = 0; /* ATMEL */
610 iowrite8(flash_table[hw->flash_vendor].cmd_program,
611 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
612 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
613 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
614 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
615 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
616 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
617 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
618 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
619 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
620 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
621 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
622 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
623 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
624 iowrite8(flash_table[hw->flash_vendor].cmd_read,
625 hw->hw_addr + REG_SPI_FLASH_OP_READ);
630 * hw - Struct containing variables accessed by shared code
636 s32 atl1_init_hw(struct atl1_hw *hw)
641 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
643 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
645 atl1_init_flash_opcode(hw);
647 if (!hw->phy_configured) {
649 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
653 ret_val = atl1_phy_leave_power_saving(hw);
657 ret_val = atl1_setup_link(hw);
664 * hw - Struct containing variables accessed by shared code
668 s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
670 struct pci_dev *pdev = hw->back->pdev;
675 ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
705 void atl1_set_mac_addr(struct atl1_hw *hw)
713 value = (((u32) hw->mac_addr[2]) << 24) |
714 (((u32) hw->mac_addr[3]) << 16) |
715 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
716 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
718 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
719 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));