Lines Matching defs:mclk
436 unsigned long mclk;
450 unsigned long mclk;
457 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
465 diff = sm501fb_round_div(mclk, divider << shift) - freq;
473 clock->mclk = mclk;
482 return clock->mclk / (clock->divider << clock->shift);
520 if (to.mclk != 288000000)
521 reg |= 0x20; /* which mclk pll is source */
532 if (to.mclk != 288000000)
533 reg |= 0x10; /* which mclk pll is source */
544 if (to.mclk != 288000000)
545 reg |= 0x10; /* which mclk pll is source */
854 if (init->mclk) {
855 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
856 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1086 .mclk = 72 * MHZ,