Lines Matching refs:itv
27 static int ivtv_yuv_prep_user_dma(struct ivtv *itv, struct ivtv_user_dma *dma,
38 int frame = atomic_read(&itv->yuv_info.next_fill_frame);
87 dma->SG_length = pci_map_sg(itv->dev, dma->SGlist, dma->page_count, PCI_DMA_TODEVICE);
94 if (itv->yuv_info.blanking_dmaptr) {
96 dma->SGarray[dma->SG_length].src = cpu_to_le32(itv->yuv_info.blanking_dmaptr);
105 ivtv_udma_sync_for_device(itv);
110 int ivtv_yuv_filter_check(struct ivtv *itv)
124 static void ivtv_yuv_filter(struct ivtv *itv, int h_filter, int v_filter_1, int v_filter_2)
187 static void ivtv_yuv_handle_horizontal(struct ivtv *itv, struct yuv_frame_info *window)
307 IVTV_DEBUG_YUV("Update reg 0x2834 %08x->%08x 0x2838 %08x->%08x\n",itv->yuv_info.reg_2834, reg_2834, itv->yuv_info.reg_2838, reg_2838);
312 IVTV_DEBUG_YUV("Update reg 0x283c %08x->%08x 0x2844 %08x->%08x\n",itv->yuv_info.reg_283c, reg_283c, itv->yuv_info.reg_2844, reg_2844);
316 IVTV_DEBUG_YUV("Update reg 0x2840 %08x->%08x 0x2848 %08x->%08x\n",itv->yuv_info.reg_2840, 0x00080514, itv->yuv_info.reg_2848, 0x00100514);
319 IVTV_DEBUG_YUV("Update reg 0x2854 %08x->%08x \n",itv->yuv_info.reg_2854, reg_2854);
323 IVTV_DEBUG_YUV("Update reg 0x285c %08x->%08x 0x2864 %08x->%08x\n",itv->yuv_info.reg_285c, reg_285c, itv->yuv_info.reg_2864, reg_2864);
326 IVTV_DEBUG_YUV("Update reg 0x2874 %08x->%08x\n",itv->yuv_info.reg_2874, reg_2874);
329 IVTV_DEBUG_YUV("Update reg 0x2870 %08x->%08x\n",itv->yuv_info.reg_2870, reg_2870);
332 IVTV_DEBUG_YUV("Update reg 0x2890 %08x->%08x\n",itv->yuv_info.reg_2890, reg_2890);
335 if (h_filter != itv->yuv_info.h_filter) {
336 ivtv_yuv_filter (itv,h_filter,-1,-1);
337 itv->yuv_info.h_filter = h_filter;
341 static void ivtv_yuv_handle_vertical(struct ivtv *itv, struct yuv_frame_info *window)
374 if (itv->yuv_info.frame_interlaced) {
491 if (itv->yuv_info.decode_height == 480)
551 IVTV_DEBUG_YUV("Update reg 0x2934 %08x->%08x 0x293c %08x->%08x\n",itv->yuv_info.reg_2934, reg_2934, itv->yuv_info.reg_293c, reg_293c);
554 IVTV_DEBUG_YUV("Update reg 0x2944 %08x->%08x 0x294c %08x->%08x\n",itv->yuv_info.reg_2944, reg_2944, itv->yuv_info.reg_294c, reg_294c);
558 /* IVTV_DEBUG_YUV("Update reg 0x2970 %08x->%08x\n",itv->yuv_info.reg_2970, 0); */
562 IVTV_DEBUG_YUV("Update reg 0x2930 %08x->%08x 0x2938 %08x->%08x\n",itv->yuv_info.reg_2930, reg_2930, itv->yuv_info.reg_2938, reg_2930);
566 IVTV_DEBUG_YUV("Update reg 0x2928 %08x->%08x 0x292c %08x->%08x\n",itv->yuv_info.reg_2928, reg_2928, itv->yuv_info.reg_292c, reg_2928+0x514);
570 IVTV_DEBUG_YUV("Update reg 0x2920 %08x->%08x 0x2924 %08x->%08x\n",itv->yuv_info.reg_2920, reg_2920, itv->yuv_info.reg_2924, 0x514+reg_2920);
574 IVTV_DEBUG_YUV("Update reg 0x2918 %08x->%08x 0x291C %08x->%08x\n",itv->yuv_info.reg_2918,reg_2918,itv->yuv_info.reg_291c,reg_291c);
577 IVTV_DEBUG_YUV("Update reg 0x296c %08x->%08x\n",itv->yuv_info.reg_296c, reg_296c);
581 IVTV_DEBUG_YUV("Update reg 0x2940 %08x->%08x 0x2948 %08x->%08x\n",itv->yuv_info.reg_2940, reg_2940, itv->yuv_info.reg_2948, reg_2940);
585 IVTV_DEBUG_YUV("Update reg 0x2950 %08x->%08x 0x2954 %08x->%08x\n",itv->yuv_info.reg_2950, reg_2950, itv->yuv_info.reg_2954, reg_2954);
589 IVTV_DEBUG_YUV("Update reg 0x2958 %08x->%08x 0x295C %08x->%08x\n",itv->yuv_info.reg_2958, reg_2958, itv->yuv_info.reg_295c, reg_295c);
592 IVTV_DEBUG_YUV("Update reg 0x2960 %08x->%08x \n",itv->yuv_info.reg_2960, reg_2960);
596 IVTV_DEBUG_YUV("Update reg 0x2964 %08x->%08x 0x2968 %08x->%08x\n",itv->yuv_info.reg_2964, reg_2964, itv->yuv_info.reg_2968, reg_2968);
599 IVTV_DEBUG_YUV("Update reg 0x289c %08x->%08x\n",itv->yuv_info.reg_289c, reg_289c);
602 if (v_filter_1 != itv->yuv_info.v_filter_1) {
603 ivtv_yuv_filter (itv,-1,v_filter_1,-1);
604 itv->yuv_info.v_filter_1 = v_filter_1;
608 if (v_filter_2 != itv->yuv_info.v_filter_2) {
609 ivtv_yuv_filter (itv,-1,-1,v_filter_2);
610 itv->yuv_info.v_filter_2 = v_filter_2;
613 itv->yuv_info.frame_interlaced_last = itv->yuv_info.frame_interlaced;
617 static u32 ivtv_yuv_window_setup (struct ivtv *itv, struct yuv_frame_info *window)
623 lace_threshold = itv->yuv_info.lace_threshold;
625 lace_threshold = itv->yuv_info.decode_height - 1;
628 switch (itv->yuv_info.lace_mode) {
630 itv->yuv_info.frame_interlaced = 0;
644 itv->yuv_info.frame_interlaced = 0;
658 itv->yuv_info.frame_interlaced = 1;
666 itv->yuv_info.frame_interlaced = 1;
743 window->dst_x += itv->yuv_info.osd_x_offset;
744 window->dst_y += itv->yuv_info.osd_y_offset;
785 if ((itv->yuv_info.old_frame_info.dst_w != window->dst_w) ||
786 (itv->yuv_info.old_frame_info.src_w != window->src_w) ||
787 (itv->yuv_info.old_frame_info.dst_x != window->dst_x) ||
788 (itv->yuv_info.old_frame_info.src_x != window->src_x) ||
789 (itv->yuv_info.old_frame_info.pan_x != window->pan_x) ||
790 (itv->yuv_info.old_frame_info.vis_w != window->vis_w)) {
794 if ((itv->yuv_info.old_frame_info.src_h != window->src_h) ||
795 (itv->yuv_info.old_frame_info.dst_h != window->dst_h) ||
796 (itv->yuv_info.old_frame_info.dst_y != window->dst_y) ||
797 (itv->yuv_info.old_frame_info.src_y != window->src_y) ||
798 (itv->yuv_info.old_frame_info.pan_y != window->pan_y) ||
799 (itv->yuv_info.old_frame_info.vis_h != window->vis_h) ||
800 (itv->yuv_info.old_frame_info.interlaced_y != window->interlaced_y) ||
801 (itv->yuv_info.old_frame_info.interlaced_uv != window->interlaced_uv)) {
809 void ivtv_yuv_work_handler (struct ivtv *itv)
814 int frame = itv->yuv_info.update_frame;
817 memcpy(&window, &itv->yuv_info.new_frame_info[frame], sizeof (window));
820 window.pan_x = itv->yuv_info.osd_x_pan;
821 window.pan_y = itv->yuv_info.osd_y_pan;
822 window.vis_w = itv->yuv_info.osd_vis_w;
823 window.vis_h = itv->yuv_info.osd_vis_h;
826 if (!(yuv_update = ivtv_yuv_window_setup (itv, &window)))
831 ivtv_yuv_handle_horizontal(itv, &window);
834 ivtv_yuv_handle_vertical(itv, &window);
836 memcpy(&itv->yuv_info.old_frame_info, &window, sizeof (itv->yuv_info.old_frame_info));
839 static void ivtv_yuv_init (struct ivtv *itv)
844 itv->yuv_info.reg_2834 = read_reg(0x02834);
845 itv->yuv_info.reg_2838 = read_reg(0x02838);
846 itv->yuv_info.reg_283c = read_reg(0x0283c);
847 itv->yuv_info.reg_2840 = read_reg(0x02840);
848 itv->yuv_info.reg_2844 = read_reg(0x02844);
849 itv->yuv_info.reg_2848 = read_reg(0x02848);
850 itv->yuv_info.reg_2854 = read_reg(0x02854);
851 itv->yuv_info.reg_285c = read_reg(0x0285c);
852 itv->yuv_info.reg_2864 = read_reg(0x02864);
853 itv->yuv_info.reg_2870 = read_reg(0x02870);
854 itv->yuv_info.reg_2874 = read_reg(0x02874);
855 itv->yuv_info.reg_2898 = read_reg(0x02898);
856 itv->yuv_info.reg_2890 = read_reg(0x02890);
858 itv->yuv_info.reg_289c = read_reg(0x0289c);
859 itv->yuv_info.reg_2918 = read_reg(0x02918);
860 itv->yuv_info.reg_291c = read_reg(0x0291c);
861 itv->yuv_info.reg_2920 = read_reg(0x02920);
862 itv->yuv_info.reg_2924 = read_reg(0x02924);
863 itv->yuv_info.reg_2928 = read_reg(0x02928);
864 itv->yuv_info.reg_292c = read_reg(0x0292c);
865 itv->yuv_info.reg_2930 = read_reg(0x02930);
866 itv->yuv_info.reg_2934 = read_reg(0x02934);
867 itv->yuv_info.reg_2938 = read_reg(0x02938);
868 itv->yuv_info.reg_293c = read_reg(0x0293c);
869 itv->yuv_info.reg_2940 = read_reg(0x02940);
870 itv->yuv_info.reg_2944 = read_reg(0x02944);
871 itv->yuv_info.reg_2948 = read_reg(0x02948);
872 itv->yuv_info.reg_294c = read_reg(0x0294c);
873 itv->yuv_info.reg_2950 = read_reg(0x02950);
874 itv->yuv_info.reg_2954 = read_reg(0x02954);
875 itv->yuv_info.reg_2958 = read_reg(0x02958);
876 itv->yuv_info.reg_295c = read_reg(0x0295c);
877 itv->yuv_info.reg_2960 = read_reg(0x02960);
878 itv->yuv_info.reg_2964 = read_reg(0x02964);
879 itv->yuv_info.reg_2968 = read_reg(0x02968);
880 itv->yuv_info.reg_296c = read_reg(0x0296c);
881 itv->yuv_info.reg_2970 = read_reg(0x02970);
883 itv->yuv_info.v_filter_1 = -1;
884 itv->yuv_info.v_filter_2 = -1;
885 itv->yuv_info.h_filter = -1;
888 itv->yuv_info.osd_x_offset = read_reg(0x02a04) & 0x00000FFF;
889 itv->yuv_info.osd_y_offset = (read_reg(0x02a04) >> 16) & 0x00000FFF;
894 itv->yuv_info.decode_height = 576;
896 itv->yuv_info.decode_height = 480;
899 if (!itv->yuv_info.osd_vis_w) itv->yuv_info.osd_vis_w = 720 - itv->yuv_info.osd_x_offset;
900 if (!itv->yuv_info.osd_vis_h) itv->yuv_info.osd_vis_h = itv->yuv_info.decode_height - itv->yuv_info.osd_y_offset;
903 itv->yuv_info.blanking_ptr = kzalloc(720*16,GFP_KERNEL);
904 if (itv->yuv_info.blanking_ptr) {
905 itv->yuv_info.blanking_dmaptr = pci_map_single(itv->dev, itv->yuv_info.blanking_ptr, 720*16, PCI_DMA_TODEVICE);
908 itv->yuv_info.blanking_dmaptr = 0;
918 set_bit(IVTV_F_I_DECODING_YUV, &itv->i_flags);
919 atomic_set(&itv->yuv_info.next_dma_frame,0);
922 int ivtv_yuv_prep_frame(struct ivtv *itv, struct ivtv_dma_frame *args)
931 if (atomic_read(&itv->yuv_info.next_dma_frame) == -1) ivtv_yuv_init(itv);
933 frame = atomic_read(&itv->yuv_info.next_fill_frame);
935 last_fill_frame = (atomic_read(&itv->yuv_info.next_dma_frame)+1) & 0x3;
944 itv->yuv_info.new_frame_info[frame].src_x = args->src.left;
945 itv->yuv_info.new_frame_info[frame].src_y = args->src.top;
946 itv->yuv_info.new_frame_info[frame].src_w = args->src.width;
947 itv->yuv_info.new_frame_info[frame].src_h = args->src.height;
948 itv->yuv_info.new_frame_info[frame].dst_x = args->dst.left;
949 itv->yuv_info.new_frame_info[frame].dst_y = args->dst.top;
950 itv->yuv_info.new_frame_info[frame].dst_w = args->dst.width;
951 itv->yuv_info.new_frame_info[frame].dst_h = args->dst.height;
952 itv->yuv_info.new_frame_info[frame].tru_x = args->dst.left;
953 itv->yuv_info.new_frame_info[frame].tru_w = args->src_width;
954 itv->yuv_info.new_frame_info[frame].tru_h = args->src_height;
958 itv->yuv_info.new_frame_info[frame].offset_y = 1;
960 itv->yuv_info.new_frame_info[frame].offset_y = 0;
963 itv->yuv_info.new_frame_info[frame].pan_x = itv->yuv_info.osd_x_pan;
964 itv->yuv_info.new_frame_info[frame].pan_y = itv->yuv_info.osd_y_pan;
965 itv->yuv_info.new_frame_info[frame].vis_w = itv->yuv_info.osd_vis_w;
966 itv->yuv_info.new_frame_info[frame].vis_h = itv->yuv_info.osd_vis_h;
968 itv->yuv_info.new_frame_info[frame].update = 0;
969 itv->yuv_info.new_frame_info[frame].interlaced_y = 0;
970 itv->yuv_info.new_frame_info[frame].interlaced_uv = 0;
972 if (memcmp (&itv->yuv_info.old_frame_info_args, &itv->yuv_info.new_frame_info[frame],
973 sizeof (itv->yuv_info.new_frame_info[frame]))) {
974 memcpy(&itv->yuv_info.old_frame_info_args, &itv->yuv_info.new_frame_info[frame], sizeof (itv->yuv_info.old_frame_info_args));
975 itv->yuv_info.new_frame_info[frame].update = 1;
980 mutex_lock(&itv->udma.lock);
982 if ((rc = ivtv_yuv_prep_user_dma(itv, &itv->udma, args)) != 0) {
983 mutex_unlock(&itv->udma.lock);
987 ivtv_udma_prepare(itv);
988 prepare_to_wait(&itv->dma_waitq, &wait, TASK_INTERRUPTIBLE);
991 while (itv->i_flags & (IVTV_F_I_UDMA_PENDING | IVTV_F_I_UDMA)) {
995 if (got_sig && test_and_clear_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags))
1000 finish_wait(&itv->dma_waitq, &wait);
1003 ivtv_udma_unmap(itv);
1007 mutex_unlock(&itv->udma.lock);
1011 atomic_set(&itv->yuv_info.next_fill_frame, next_fill_frame);
1013 mutex_unlock(&itv->udma.lock);
1017 void ivtv_yuv_close(struct ivtv *itv)
1022 ivtv_waitq(&itv->vsync_waitq);
1024 atomic_set(&itv->yuv_info.next_dma_frame, -1);
1025 atomic_set(&itv->yuv_info.next_fill_frame, 0);
1032 write_reg(itv->yuv_info.reg_2898 | 0x01000000, 0x2898);
1034 write_reg(itv->yuv_info.reg_2834, 0x02834);
1035 write_reg(itv->yuv_info.reg_2838, 0x02838);
1036 write_reg(itv->yuv_info.reg_283c, 0x0283c);
1037 write_reg(itv->yuv_info.reg_2840, 0x02840);
1038 write_reg(itv->yuv_info.reg_2844, 0x02844);
1039 write_reg(itv->yuv_info.reg_2848, 0x02848);
1040 write_reg(itv->yuv_info.reg_2854, 0x02854);
1041 write_reg(itv->yuv_info.reg_285c, 0x0285c);
1042 write_reg(itv->yuv_info.reg_2864, 0x02864);
1043 write_reg(itv->yuv_info.reg_2870, 0x02870);
1044 write_reg(itv->yuv_info.reg_2874, 0x02874);
1045 write_reg(itv->yuv_info.reg_2890, 0x02890);
1046 write_reg(itv->yuv_info.reg_289c, 0x0289c);
1048 write_reg(itv->yuv_info.reg_2918, 0x02918);
1049 write_reg(itv->yuv_info.reg_291c, 0x0291c);
1050 write_reg(itv->yuv_info.reg_2920, 0x02920);
1051 write_reg(itv->yuv_info.reg_2924, 0x02924);
1052 write_reg(itv->yuv_info.reg_2928, 0x02928);
1053 write_reg(itv->yuv_info.reg_292c, 0x0292c);
1054 write_reg(itv->yuv_info.reg_2930, 0x02930);
1055 write_reg(itv->yuv_info.reg_2934, 0x02934);
1056 write_reg(itv->yuv_info.reg_2938, 0x02938);
1057 write_reg(itv->yuv_info.reg_293c, 0x0293c);
1058 write_reg(itv->yuv_info.reg_2940, 0x02940);
1059 write_reg(itv->yuv_info.reg_2944, 0x02944);
1060 write_reg(itv->yuv_info.reg_2948, 0x02948);
1061 write_reg(itv->yuv_info.reg_294c, 0x0294c);
1062 write_reg(itv->yuv_info.reg_2950, 0x02950);
1063 write_reg(itv->yuv_info.reg_2954, 0x02954);
1064 write_reg(itv->yuv_info.reg_2958, 0x02958);
1065 write_reg(itv->yuv_info.reg_295c, 0x0295c);
1066 write_reg(itv->yuv_info.reg_2960, 0x02960);
1067 write_reg(itv->yuv_info.reg_2964, 0x02964);
1068 write_reg(itv->yuv_info.reg_2968, 0x02968);
1069 write_reg(itv->yuv_info.reg_296c, 0x0296c);
1070 write_reg(itv->yuv_info.reg_2970, 0x02970);
1075 if ((itv->yuv_info.reg_2834 & 0x0000FFFF) == (itv->yuv_info.reg_2834 >> 16)) {
1081 h_filter = ((itv->yuv_info.reg_2834 << 16) / (itv->yuv_info.reg_2834 >> 16)) >> 15;
1088 if ((itv->yuv_info.reg_2918 & 0x0000FFFF) == (itv->yuv_info.reg_2918 >> 16)) {
1095 v_filter_1 = ((itv->yuv_info.reg_2918 << 16) / (itv->yuv_info.reg_2918 >> 16)) >> 15;
1103 ivtv_yuv_filter (itv,h_filter,v_filter_1,v_filter_2);
1112 if (itv->yuv_info.blanking_ptr) {
1113 kfree (itv->yuv_info.blanking_ptr);
1114 itv->yuv_info.blanking_ptr = NULL;
1115 pci_unmap_single(itv->dev, itv->yuv_info.blanking_dmaptr, 720*16, PCI_DMA_TODEVICE);
1119 itv->yuv_info.old_frame_info.src_w = 0;
1120 itv->yuv_info.old_frame_info.src_h = 0;
1121 itv->yuv_info.old_frame_info_args.src_w = 0;
1122 itv->yuv_info.old_frame_info_args.src_h = 0;
1125 clear_bit(IVTV_F_I_DECODING_YUV, &itv->i_flags);