Lines Matching refs:itv
44 static void ivtv_pio_work_handler(struct ivtv *itv)
46 struct ivtv_stream *s = &itv->streams[itv->cur_pio_stream];
52 if (itv->cur_pio_stream < 0 || itv->cur_pio_stream >= IVTV_MAX_STREAMS ||
54 itv->cur_pio_stream = -1;
67 memcpy_fromio(buf->buf, itv->dec_mem + s->PIOarray[i].src - IVTV_DECODER_OFFSET, size);
70 memcpy_fromio(buf->buf, itv->enc_mem + s->PIOarray[i].src, size);
81 struct ivtv *itv = container_of(work, struct ivtv, irq_work_queue);
85 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags))
86 ivtv_pio_work_handler(itv);
88 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags))
89 ivtv_vbi_work_handler(itv);
91 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags))
92 ivtv_yuv_work_handler(itv);
101 struct ivtv *itv = s->itv;
142 if (itv->has_cx23415)
147 size = itv->vbi.enc_size * itv->vbi.fpi;
148 offset = read_enc(itv->vbi.enc_start - 4) + 12;
157 size = read_dec(itv->vbi.dec_start + 4) + 8;
158 offset = read_dec(itv->vbi.dec_start) + itv->vbi.dec_start;
169 if (itv->has_cx23415 && (s->type == IVTV_ENC_STREAM_TYPE_PCM ||
238 struct ivtv *itv = s->itv;
272 if (itv->has_cx23415 && (s->type == IVTV_ENC_STREAM_TYPE_PCM ||
299 ivtv_process_vbi_data(itv, buf, 0, s->type);
314 struct ivtv *itv = s->itv;
317 u32 y_size = itv->params.height * itv->params.width;
353 spin_lock_irqsave(&itv->dma_reg_lock, flags);
354 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags)) {
361 spin_unlock_irqrestore(&itv->dma_reg_lock, flags);
367 struct ivtv *itv = s->itv;
368 struct ivtv_stream *s_vbi = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
397 itv->vbi.dma_offset = s_vbi->dma_offset;
411 set_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags);
412 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
413 set_bit(IVTV_F_I_PIO, &itv->i_flags);
414 itv->cur_pio_stream = s->type;
421 set_bit(IVTV_F_I_DMA, &itv->i_flags);
422 itv->cur_dma_stream = s->type;
423 itv->dma_timer.expires = jiffies + HZ / 10;
424 add_timer(&itv->dma_timer);
430 struct ivtv *itv = s->itv;
438 set_bit(IVTV_F_I_DMA, &itv->i_flags);
439 itv->cur_dma_stream = s->type;
440 itv->dma_timer.expires = jiffies + HZ / 10;
441 add_timer(&itv->dma_timer);
444 static void ivtv_irq_dma_read(struct ivtv *itv)
451 del_timer(&itv->dma_timer);
456 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
457 if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) {
458 s = &itv->streams[IVTV_DEC_STREAM_TYPE_YUV];
462 s = &itv->streams[IVTV_DEC_STREAM_TYPE_MPG];
475 ivtv_vapi(itv, CX2341X_DEC_SCHED_DMA_FROM_HOST, 3, 0, s->q_dma.bytesused,
485 clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
486 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
487 itv->cur_dma_stream = -1;
488 wake_up(&itv->dma_waitq);
491 static void ivtv_irq_enc_dma_complete(struct ivtv *itv)
496 del_timer(&itv->dma_timer);
497 ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data);
499 if (test_and_clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags))
503 s = &itv->streams[ivtv_stream_map[data[1]]];
507 ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, data[1]);
510 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
511 itv->cur_dma_stream = -1;
517 s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
519 s->dma_offset = itv->vbi.dma_offset;
523 wake_up(&itv->dma_waitq);
526 static void ivtv_irq_enc_pio_complete(struct ivtv *itv)
530 if (itv->cur_pio_stream < 0 || itv->cur_pio_stream >= IVTV_MAX_STREAMS) {
531 itv->cur_pio_stream = -1;
534 s = &itv->streams[itv->cur_pio_stream];
537 clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
538 clear_bit(IVTV_F_I_PIO, &itv->i_flags);
539 itv->cur_pio_stream = -1;
542 ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 0);
544 ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 1);
546 ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 2);
547 clear_bit(IVTV_F_I_PIO, &itv->i_flags);
551 s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
553 s->dma_offset = itv->vbi.dma_offset;
557 wake_up(&itv->dma_waitq);
560 static void ivtv_irq_dma_err(struct ivtv *itv)
564 del_timer(&itv->dma_timer);
565 ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data);
567 read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream);
568 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) &&
569 itv->cur_dma_stream >= 0 && itv->cur_dma_stream < IVTV_MAX_STREAMS) {
570 struct ivtv_stream *s = &itv->streams[itv->cur_dma_stream];
580 clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
581 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
582 itv->cur_dma_stream = -1;
583 wake_up(&itv->dma_waitq);
586 static void ivtv_irq_enc_start_cap(struct ivtv *itv)
592 ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA, data);
600 clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
601 s = &itv->streams[ivtv_stream_map[data[0]]];
607 static void ivtv_irq_enc_vbi_cap(struct ivtv *itv)
609 struct ivtv_stream *s_mpg = &itv->streams[IVTV_ENC_STREAM_TYPE_MPG];
614 s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
637 set_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
642 static void ivtv_irq_dec_vbi_reinsert(struct ivtv *itv)
645 struct ivtv_stream *s = &itv->streams[IVTV_DEC_STREAM_TYPE_VBI];
654 static void ivtv_irq_dec_data_req(struct ivtv *itv)
660 ivtv_api_get_data(&itv->dec_mbox, IVTV_MBOX_DMA, data);
662 if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) {
663 itv->dma_data_req_size = itv->params.width * itv->params.height * 3 / 2;
664 itv->dma_data_req_offset = data[1] ? data[1] : yuv_offset[0];
665 s = &itv->streams[IVTV_DEC_STREAM_TYPE_YUV];
668 itv->dma_data_req_size = data[2] >= 0x10000 ? 0x10000 : data[2];
669 itv->dma_data_req_offset = data[1];
670 s = &itv->streams[IVTV_DEC_STREAM_TYPE_MPG];
673 itv->dma_data_req_offset, itv->dma_data_req_size);
674 if (itv->dma_data_req_size == 0 || s->q_full.bytesused < itv->dma_data_req_size) {
679 ivtv_queue_move(s, &s->q_full, NULL, &s->q_predma, itv->dma_data_req_size);
680 ivtv_dma_stream_dec_prepare(s, itv->dma_data_req_offset + IVTV_DECODER_OFFSET, 0);
684 static void ivtv_irq_vsync(struct ivtv *itv)
694 int last_dma_frame = atomic_read(&itv->yuv_info.next_dma_frame);
698 if (((frame ^ itv->yuv_info.lace_sync_field) == 0 && ((itv->lastVsyncFrame & 1) ^ itv->yuv_info.lace_sync_field)) ||
699 (frame != (itv->lastVsyncFrame & 1) && !itv->yuv_info.frame_interlaced)) {
702 if (next_dma_frame >= 0 && next_dma_frame != atomic_read(&itv->yuv_info.next_fill_frame)) {
708 atomic_set(&itv->yuv_info.next_dma_frame, next_dma_frame);
711 if (frame != (itv->lastVsyncFrame & 1)) {
712 struct ivtv_stream *s = ivtv_get_output_stream(itv);
714 itv->lastVsyncFrame += 1;
716 clear_bit(IVTV_F_I_VALID_DEC_TIMINGS, &itv->i_flags);
717 clear_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);
720 set_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);
722 if (test_bit(IVTV_F_I_EV_VSYNC_ENABLED, &itv->i_flags)) {
723 set_bit(IVTV_F_I_EV_VSYNC, &itv->i_flags);
724 wake_up(&itv->event_waitq);
726 wake_up(&itv->vsync_waitq);
732 set_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags);
733 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
737 if ((itv->yuv_info.yuv_forced_update || itv->yuv_info.new_frame_info[last_dma_frame].update) && last_dma_frame != -1) {
738 if (!itv->yuv_info.new_frame_info[last_dma_frame].update)
741 if (itv->yuv_info.new_frame_info[last_dma_frame].src_w) {
742 itv->yuv_info.update_frame = last_dma_frame;
743 itv->yuv_info.new_frame_info[last_dma_frame].update = 0;
744 itv->yuv_info.yuv_forced_update = 0;
745 set_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags);
746 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
756 struct ivtv *itv = (struct ivtv *)dev_id;
762 spin_lock(&itv->dma_reg_lock);
766 combo = ~itv->irqmask & stat;
775 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
777 if ((itv->lastVsyncFrame & 1) != (read_reg(0x28c0) & 1)) {
786 spin_unlock(&itv->dma_reg_lock);
801 ivtv_irq_dma_read(itv);
805 ivtv_irq_enc_dma_complete(itv);
809 ivtv_irq_enc_pio_complete(itv);
813 ivtv_irq_dma_err(itv);
817 ivtv_irq_enc_start_cap(itv);
821 ivtv_irq_enc_vbi_cap(itv);
825 ivtv_irq_dec_vbi_reinsert(itv);
830 set_bit(IVTV_F_I_EOS, &itv->i_flags);
831 wake_up(&itv->cap_w);
835 ivtv_irq_dec_data_req(itv);
839 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
840 ivtv_irq_vsync(itv);
845 /*ivtv_vapi(itv, CX2341X_ENC_REFRESH_INPUT, 0); */
852 if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_DMA, &itv->i_flags)) {
854 int idx = (i + itv->irq_rr_idx++) % IVTV_MAX_STREAMS;
855 struct ivtv_stream *s = &itv->streams[idx];
865 if (i == IVTV_MAX_STREAMS && test_and_clear_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags)) {
866 ivtv_udma_start(itv);
870 if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_PIO, &itv->i_flags)) {
872 int idx = (i + itv->irq_rr_idx++) % IVTV_MAX_STREAMS;
873 struct ivtv_stream *s = &itv->streams[idx];
883 if (test_and_clear_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags))
884 queue_work(itv->irq_work_queues, &itv->irq_work_queue);
886 spin_unlock(&itv->dma_reg_lock);
897 struct ivtv *itv = (struct ivtv *)arg;
899 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))
901 IVTV_ERR("DMA TIMEOUT %08x %d\n", read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream);
904 clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
905 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
906 itv->cur_dma_stream = -1;
907 wake_up(&itv->dma_waitq);