Lines Matching refs:bw
251 timf = state->cfg.bw->timf;
282 static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw)
284 dib7000m_write_word(state, 18, ((bw->internal*1000) >> 16) & 0xffff);
285 dib7000m_write_word(state, 19, (bw->internal*1000) & 0xffff);
286 dib7000m_write_word(state, 21, (bw->ifreq >> 16) & 0xffff);
287 dib7000m_write_word(state, 22, bw->ifreq & 0xffff);
289 dib7000m_write_word(state, 928, bw->sad_cfg);
294 const struct dibx000_bandwidth_config *bw = state->cfg.bw;
298 reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) |
299 (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) |
300 (bw->enable_refdiv << 1) | (0 << 0);
301 reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset;
314 reg_907 |= (bw->pll_ratio & 0x3f) << 9;
315 reg_910 |= (bw->pll_prediv << 5);
322 dib7000m_reset_pll_common(state, bw);
327 const struct dibx000_bandwidth_config *bw = state->cfg.bw;
330 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
335 (bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) |
336 (bw->pll_bypass << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0));
339 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7));
341 dib7000m_reset_pll_common(state, bw);
530 dprintk("-D- Updated timf_frequency: %d (default: %d)\n",state->timf, state->cfg.bw->timf);
658 value = 30 * state->cfg.bw->internal;
661 value = 100 * state->cfg.bw->internal;
664 value = 500 * state->cfg.bw->internal;