Lines Matching refs:bcs
56 GetFreeFifoBytes(struct BCState *bcs)
60 if (bcs->hw.hfc.f1 == bcs->hw.hfc.f2)
61 return (bcs->cs->hw.hfc.fifosize);
62 s = bcs->hw.hfc.send[bcs->hw.hfc.f1] - bcs->hw.hfc.send[bcs->hw.hfc.f2];
64 s += bcs->cs->hw.hfc.fifosize;
65 s = bcs->cs->hw.hfc.fifosize - s;
70 ReadZReg(struct BCState *bcs, u_char reg)
74 WaitNoBusy(bcs->cs);
75 val = 256 * bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_HIGH);
76 WaitNoBusy(bcs->cs);
77 val += bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_LOW);
82 hfc_clear_fifo(struct BCState *bcs)
84 struct IsdnCardState *cs = bcs->cs;
91 cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
98 cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
101 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
102 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
107 bcs->channel, f1, f2);
115 bcs->channel, z1, z2, rcnt);
116 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
125 HFC_CHANNEL(bcs->channel));
128 cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
131 cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
134 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
135 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
143 hfc_empty_fifo(struct BCState *bcs, int count)
147 struct IsdnCardState *cs = bcs->cs;
158 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
163 HFC_CHANNEL(bcs->channel));
167 if ((count < 4) && (bcs->mode != L1_MODE_TRANS)) {
170 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
175 HFC_CHANNEL(bcs->channel));
178 bcs->err_inv++;
182 if (bcs->mode == L1_MODE_TRANS)
191 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
198 printk(KERN_WARNING "HFC FIFO channel %d BUSY Error\n", bcs->channel);
200 if (bcs->mode != L1_MODE_TRANS) {
203 HFC_CHANNEL(bcs->channel));
208 if (bcs->mode != L1_MODE_TRANS) {
217 bcs->channel, chksum, stat);
223 bcs->err_crc++;
228 HFC_CHANNEL(bcs->channel));
236 hfc_fill_fifo(struct BCState *bcs)
238 struct IsdnCardState *cs = bcs->cs;
244 if (!bcs->tx_skb)
246 if (bcs->tx_skb->len <= 0)
249 cip = HFC_CIP | HFC_F1 | HFC_SEND | HFC_CHANNEL(bcs->channel);
255 if (bcs->mode != L1_MODE_TRANS) {
256 bcs->hw.hfc.f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
257 cip = HFC_CIP | HFC_F2 | HFC_SEND | HFC_CHANNEL(bcs->channel);
259 bcs->hw.hfc.f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
260 bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(bcs, HFC_Z1 | HFC_SEND | HFC_CHANNEL(bcs->channel));
263 bcs->channel, bcs->hw.hfc.f1, bcs->hw.hfc.f2,
264 bcs->hw.hfc.send[bcs->hw.hfc.f1]);
265 fcnt = bcs->hw.hfc.f1 - bcs->hw.hfc.f2;
273 count = GetFreeFifoBytes(bcs);
277 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
278 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
285 bcs->channel, bcs->tx_skb->len,
287 if (count < bcs->tx_skb->len) {
292 cip = HFC_CIP | HFC_FIFO_IN | HFC_SEND | HFC_CHANNEL(bcs->channel);
294 while ((idx < bcs->tx_skb->len) && WaitNoBusy(cs))
295 cs->BC_Write_Reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
296 if (idx != bcs->tx_skb->len) {
298 printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
300 count = bcs->tx_skb->len;
301 bcs->tx_cnt -= count;
302 if (PACKET_NOACK == bcs->tx_skb->pkt_type)
304 dev_kfree_skb_any(bcs->tx_skb);
305 bcs->tx_skb = NULL;
306 if (bcs->mode != L1_MODE_TRANS) {
309 cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F1_INC | HFC_SEND | HFC_CHANNEL(bcs->channel));
311 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
314 spin_lock_irqsave(&bcs->aclock, flags);
315 bcs->ackcnt += count;
316 spin_unlock_irqrestore(&bcs->aclock, flags);
317 schedule_event(bcs, B_ACKPENDING);
319 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
325 main_irq_hfc(struct BCState *bcs)
327 struct IsdnCardState *cs = bcs->cs;
335 cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
342 if (bcs->mode == L1_MODE_HDLC) {
344 cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
350 bcs->channel, f1, f2);
354 if (receive || (bcs->mode == L1_MODE_TRANS)) {
356 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
357 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
361 if ((bcs->mode == L1_MODE_HDLC) || (rcnt)) {
365 bcs->channel, z1, z2, rcnt);
367 if ((skb = hfc_empty_fifo(bcs, rcnt))) {
368 skb_queue_tail(&bcs->rqueue, skb);
369 schedule_event(bcs, B_RCVBUFREADY);
374 if (bcs->tx_skb) {
376 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
377 hfc_fill_fifo(bcs);
378 if (test_bit(BC_FLG_BUSY, &bcs->Flag))
381 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
383 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
384 hfc_fill_fifo(bcs);
385 if (test_bit(BC_FLG_BUSY, &bcs->Flag))
389 schedule_event(bcs, B_XMTBUFREADY);
398 mode_hfc(struct BCState *bcs, int mode, int bc)
400 struct IsdnCardState *cs = bcs->cs;
404 mode, bc, bcs->channel);
405 bcs->mode = mode;
406 bcs->channel = bc;
422 hfc_clear_fifo(bcs); /* complete fifo clear */
448 hfc_clear_fifo(bcs);
454 struct BCState *bcs = st->l1.bcs;
460 spin_lock_irqsave(&bcs->cs->lock, flags);
461 if (bcs->tx_skb) {
462 skb_queue_tail(&bcs->squeue, skb);
464 bcs->tx_skb = skb;
465 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
466 bcs->cs->BC_Send_Data(bcs);
468 spin_unlock_irqrestore(&bcs->cs->lock, flags);
471 spin_lock_irqsave(&bcs->cs->lock, flags);
472 if (bcs->tx_skb) {
475 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
476 bcs->tx_skb = skb;
477 bcs->cs->BC_Send_Data(bcs);
479 spin_unlock_irqrestore(&bcs->cs->lock, flags);
482 if (!bcs->tx_skb) {
489 spin_lock_irqsave(&bcs->cs->lock, flags);
490 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
491 mode_hfc(bcs, st->l1.mode, st->l1.bc);
492 spin_unlock_irqrestore(&bcs->cs->lock, flags);
499 spin_lock_irqsave(&bcs->cs->lock, flags);
500 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
501 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
502 mode_hfc(bcs, 0, st->l1.bc);
503 spin_unlock_irqrestore(&bcs->cs->lock, flags);
511 close_hfcstate(struct BCState *bcs)
513 mode_hfc(bcs, 0, bcs->channel);
514 if (test_bit(BC_FLG_INIT, &bcs->Flag)) {
515 skb_queue_purge(&bcs->rqueue);
516 skb_queue_purge(&bcs->squeue);
517 if (bcs->tx_skb) {
518 dev_kfree_skb_any(bcs->tx_skb);
519 bcs->tx_skb = NULL;
520 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
523 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
527 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
529 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
530 skb_queue_head_init(&bcs->rqueue);
531 skb_queue_head_init(&bcs->squeue);
533 bcs->tx_skb = NULL;
534 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
535 bcs->event = 0;
536 bcs->tx_cnt = 0;
541 setstack_hfc(struct PStack *st, struct BCState *bcs)
543 bcs->channel = st->l1.bc;
544 if (open_hfcstate(st->l1.hardware, bcs))
546 st->l1.bcs = bcs;
549 bcs->st = st;
555 init_send(struct BCState *bcs)
559 if (!(bcs->hw.hfc.send = kmalloc(32 * sizeof(unsigned int), GFP_ATOMIC))) {
565 bcs->hw.hfc.send[i] = 0x1fff;
571 init_send(&cs->bcs[0]);
572 init_send(&cs->bcs[1]);
574 cs->bcs[0].BC_SetStack = setstack_hfc;
575 cs->bcs[1].BC_SetStack = setstack_hfc;
576 cs->bcs[0].BC_Close = close_hfcstate;
577 cs->bcs[1].BC_Close = close_hfcstate;
578 mode_hfc(cs->bcs, 0, 0);
579 mode_hfc(cs->bcs + 1, 0, 0);
585 kfree(cs->bcs[0].hw.hfc.send);
586 cs->bcs[0].hw.hfc.send = NULL;
587 kfree(cs->bcs[1].hw.hfc.send);
588 cs->bcs[1].hw.hfc.send = NULL;