Lines Matching defs:bcs
166 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
167 return(&cs->bcs[0]);
168 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
169 return(&cs->bcs[1]);
175 write_ctrl(struct BCState *bcs, int which) {
177 if (bcs->cs->debug & L1_DEB_HSCX)
178 debugl1(bcs->cs, "hdlc %c wr%x ctrl %x",
179 'A' + bcs->channel, which, bcs->hw.hdlc.ctrl.ctrl);
180 if (bcs->cs->subtyp == AVM_FRITZ_PCI) {
181 WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl);
184 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 2,
185 bcs->hw.hdlc.ctrl.sr.mode);
187 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 1,
188 bcs->hw.hdlc.ctrl.sr.xml);
190 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS,
191 bcs->hw.hdlc.ctrl.sr.cmd);
196 modehdlc(struct BCState *bcs, int mode, int bc)
198 struct IsdnCardState *cs = bcs->cs;
199 int hdlc = bcs->channel;
203 'A' + hdlc, bcs->mode, mode, hdlc, bc);
204 bcs->hw.hdlc.ctrl.ctrl = 0;
207 bcs->mode = 1;
208 bcs->channel = bc;
211 if (bcs->mode == L1_MODE_NULL)
213 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
214 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
215 write_ctrl(bcs, 5);
216 bcs->mode = L1_MODE_NULL;
217 bcs->channel = bc;
220 bcs->mode = mode;
221 bcs->channel = bc;
222 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
223 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
224 write_ctrl(bcs, 5);
225 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
226 write_ctrl(bcs, 1);
227 bcs->hw.hdlc.ctrl.sr.cmd = 0;
228 schedule_event(bcs, B_XMTBUFREADY);
231 bcs->mode = mode;
232 bcs->channel = bc;
233 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
234 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_ITF_FLG;
235 write_ctrl(bcs, 5);
236 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
237 write_ctrl(bcs, 1);
238 bcs->hw.hdlc.ctrl.sr.cmd = 0;
239 schedule_event(bcs, B_XMTBUFREADY);
245 hdlc_empty_fifo(struct BCState *bcs, int count)
249 u_char idx = bcs->channel ? AVM_HDLC_2 : AVM_HDLC_1;
251 struct IsdnCardState *cs = bcs->cs;
255 if (bcs->hw.hdlc.rcvidx + count > HSCX_BUFMAX) {
260 p = bcs->hw.hdlc.rcvbuf + bcs->hw.hdlc.rcvidx;
262 bcs->hw.hdlc.rcvidx += count;
285 char *t = bcs->blog;
290 bcs->channel ? 'B' : 'A', count);
292 debugl1(cs, bcs->blog);
297 hdlc_fill_fifo(struct BCState *bcs)
299 struct IsdnCardState *cs = bcs->cs;
307 if (!bcs->tx_skb)
309 if (bcs->tx_skb->len <= 0)
312 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XME;
313 if (bcs->tx_skb->len > fifo_size) {
316 count = bcs->tx_skb->len;
317 if (bcs->mode != L1_MODE_TRANS)
318 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XME;
321 debugl1(cs, "hdlc_fill_fifo %d/%ld", count, bcs->tx_skb->len);
322 p = bcs->tx_skb->data;
324 skb_pull(bcs->tx_skb, count);
325 bcs->tx_cnt -= count;
326 bcs->hw.hdlc.count += count;
327 bcs->hw.hdlc.ctrl.sr.xml = ((count == fifo_size) ? 0 : count);
328 write_ctrl(bcs, 3); /* sets the correct index too */
349 char *t = bcs->blog;
354 bcs->channel ? 'B' : 'A', count);
356 debugl1(cs, bcs->blog);
361 HDLC_irq(struct BCState *bcs, u_int stat) {
365 if (bcs->cs->debug & L1_DEB_HSCX)
366 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
369 if (bcs->cs->debug & L1_DEB_HSCX)
370 debugl1(bcs->cs, "RDO");
372 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
373 bcs->hw.hdlc.ctrl.sr.xml = 0;
374 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_RRS;
375 write_ctrl(bcs, 1);
376 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_RRS;
377 write_ctrl(bcs, 1);
378 bcs->hw.hdlc.rcvidx = 0;
382 hdlc_empty_fifo(bcs, len);
383 if ((stat & HDLC_STAT_RME) || (bcs->mode == L1_MODE_TRANS)) {
385 (bcs->mode == L1_MODE_TRANS)) {
386 if (!(skb = dev_alloc_skb(bcs->hw.hdlc.rcvidx)))
389 memcpy(skb_put(skb, bcs->hw.hdlc.rcvidx),
390 bcs->hw.hdlc.rcvbuf, bcs->hw.hdlc.rcvidx);
391 skb_queue_tail(&bcs->rqueue, skb);
393 bcs->hw.hdlc.rcvidx = 0;
394 schedule_event(bcs, B_RCVBUFREADY);
396 if (bcs->cs->debug & L1_DEB_HSCX)
397 debugl1(bcs->cs, "invalid frame");
399 debugl1(bcs->cs, "ch%d invalid frame %#x", bcs->channel, stat);
400 bcs->hw.hdlc.rcvidx = 0;
409 if (bcs->tx_skb) {
410 skb_push(bcs->tx_skb, bcs->hw.hdlc.count);
411 bcs->tx_cnt += bcs->hw.hdlc.count;
412 bcs->hw.hdlc.count = 0;
413 if (bcs->cs->debug & L1_DEB_WARN)
414 debugl1(bcs->cs, "ch%d XDU", bcs->channel);
415 } else if (bcs->cs->debug & L1_DEB_WARN)
416 debugl1(bcs->cs, "ch%d XDU without skb", bcs->channel);
417 bcs->hw.hdlc.ctrl.sr.xml = 0;
418 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XRS;
419 write_ctrl(bcs, 1);
420 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XRS;
421 write_ctrl(bcs, 1);
422 hdlc_fill_fifo(bcs);
424 if (bcs->tx_skb) {
425 if (bcs->tx_skb->len) {
426 hdlc_fill_fifo(bcs);
429 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
430 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
432 spin_lock_irqsave(&bcs->aclock, flags);
433 bcs->ackcnt += bcs->hw.hdlc.count;
434 spin_unlock_irqrestore(&bcs->aclock, flags);
435 schedule_event(bcs, B_ACKPENDING);
437 dev_kfree_skb_irq(bcs->tx_skb);
438 bcs->hw.hdlc.count = 0;
439 bcs->tx_skb = NULL;
442 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
443 bcs->hw.hdlc.count = 0;
444 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
445 hdlc_fill_fifo(bcs);
447 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
448 schedule_event(bcs, B_XMTBUFREADY);
457 struct BCState *bcs;
467 if (!(bcs = Sel_BCS(cs, 0))) {
471 HDLC_irq(bcs, stat);
481 if (!(bcs = Sel_BCS(cs, 1))) {
485 HDLC_irq(bcs, stat);
492 struct BCState *bcs = st->l1.bcs;
498 spin_lock_irqsave(&bcs->cs->lock, flags);
499 if (bcs->tx_skb) {
500 skb_queue_tail(&bcs->squeue, skb);
502 bcs->tx_skb = skb;
503 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
504 bcs->hw.hdlc.count = 0;
505 bcs->cs->BC_Send_Data(bcs);
507 spin_unlock_irqrestore(&bcs->cs->lock, flags);
510 spin_lock_irqsave(&bcs->cs->lock, flags);
511 if (bcs->tx_skb) {
514 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
515 bcs->tx_skb = skb;
516 bcs->hw.hdlc.count = 0;
517 bcs->cs->BC_Send_Data(bcs);
519 spin_unlock_irqrestore(&bcs->cs->lock, flags);
522 if (!bcs->tx_skb) {
529 spin_lock_irqsave(&bcs->cs->lock, flags);
530 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
531 modehdlc(bcs, st->l1.mode, st->l1.bc);
532 spin_unlock_irqrestore(&bcs->cs->lock, flags);
539 spin_lock_irqsave(&bcs->cs->lock, flags);
540 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
541 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
542 modehdlc(bcs, 0, st->l1.bc);
543 spin_unlock_irqrestore(&bcs->cs->lock, flags);
550 close_hdlcstate(struct BCState *bcs)
552 modehdlc(bcs, 0, 0);
553 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
554 kfree(bcs->hw.hdlc.rcvbuf);
555 bcs->hw.hdlc.rcvbuf = NULL;
556 kfree(bcs->blog);
557 bcs->blog = NULL;
558 skb_queue_purge(&bcs->rqueue);
559 skb_queue_purge(&bcs->squeue);
560 if (bcs->tx_skb) {
561 dev_kfree_skb_any(bcs->tx_skb);
562 bcs->tx_skb = NULL;
563 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
569 open_hdlcstate(struct IsdnCardState *cs, struct BCState *bcs)
571 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
572 if (!(bcs->hw.hdlc.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
577 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
579 "HiSax: No memory for bcs->blog\n");
580 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
581 kfree(bcs->hw.hdlc.rcvbuf);
582 bcs->hw.hdlc.rcvbuf = NULL;
585 skb_queue_head_init(&bcs->rqueue);
586 skb_queue_head_init(&bcs->squeue);
588 bcs->tx_skb = NULL;
589 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
590 bcs->event = 0;
591 bcs->hw.hdlc.rcvidx = 0;
592 bcs->tx_cnt = 0;
597 setstack_hdlc(struct PStack *st, struct BCState *bcs)
599 bcs->channel = st->l1.bc;
600 if (open_hdlcstate(st->l1.hardware, bcs))
602 st->l1.bcs = bcs;
605 bcs->st = st;
614 cs->bcs[0].BC_SetStack = setstack_hdlc;
615 cs->bcs[1].BC_SetStack = setstack_hdlc;
616 cs->bcs[0].BC_Close = close_hdlcstate;
617 cs->bcs[1].BC_Close = close_hdlcstate;
618 modehdlc(cs->bcs, -1, 0);
619 modehdlc(cs->bcs + 1, -1, 1);