Lines Matching defs:dd
334 * @dd: the infinipath device
343 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
351 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
361 ipath_dev_err(dd, "Read of hardware error status failed "
372 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
375 hwerrs &= dd->ipath_hwerrmask;
381 if ((hwerrs & ~(dd->ipath_lasthwerror |
386 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
388 dd->ipath_lasthwerror |= hwerrs;
390 if (hwerrs & ~dd->ipath_hwe_bitsextant)
391 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
393 (hwerrs & ~dd->ipath_hwe_bitsextant));
395 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
405 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
415 if (dd->ipath_flags & IPATH_INITTED) {
416 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
417 ipath_setup_pe_setextled(dd,
420 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
422 dd->ipath_serial);
430 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
431 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
432 dd->ipath_flags &= ~IPATH_INITTED;
436 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
437 dd->ipath_control);
447 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
448 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
449 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
450 dd->ipath_hwerrmask);
478 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
479 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
480 dd->ipath_hwerrmask);
488 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
489 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
490 dd->ipath_hwerrmask);
494 ipath_dev_err(dd, "%s hardware error\n", msg);
495 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
500 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
507 * @dd: the infinipath device
513 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
517 u8 boardrev = dd->ipath_boardrev;
543 ipath_dev_err(dd,
553 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
554 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
555 dd->ipath_majrev, dd->ipath_minrev);
565 * @dd: the infinipath device
573 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
578 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
581 ipath_dev_err(dd, "MemBIST did not complete!\n");
587 if (!dd->ipath_boardrev) // no PLL for Emulator
590 if (dd->ipath_minrev < 2) {
593 dd->ipath_hwerrmask = val;
598 * @dd: the infinipath device
600 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
607 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
611 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
615 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
616 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
621 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
631 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
633 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
645 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
647 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
655 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
657 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
659 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
673 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
677 val |= dd->ipath_rx_pol_inv <<
680 if (dd->ipath_minrev >= 2) {
692 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
694 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
702 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
708 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
710 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
712 if (!ipath_waitfor_mdio_cmdready(dd)) {
714 dd, dd->ipath_kregs->kr_mdio,
717 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
732 * @dd: the infinipath device
735 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
737 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
742 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
745 static int ipath_pe_intconfig(struct ipath_devdata *dd)
755 chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
758 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
759 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
760 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
761 dd->ipath_gpio_mask);
768 * @dd: the infinipath device
787 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
797 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
804 dd->ipath_extctrl = extctl;
805 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
810 * @dd: the infinipath device
818 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
820 dd->ipath_msi_lo = 0; /* just in case unload fails */
821 pci_disable_msi(dd->pcidev);
826 * @dd: the infinipath device
844 static int ipath_setup_pe_config(struct ipath_devdata *dd,
849 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
850 ret = pci_enable_msi(dd->pcidev);
852 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
855 dd->ipath_irq = pdev->irq;
857 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
859 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
860 &dd->ipath_msi_lo);
861 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
862 &dd->ipath_msi_hi);
863 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
866 pci_read_config_word(dd->pcidev,
869 &dd->ipath_msi_data);
871 "0x%x, control=0x%x\n", dd->ipath_msi_data,
876 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
877 &dd->ipath_pci_cacheline);
879 ipath_dev_err(dd, "Can't find MSI capability, "
881 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
883 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
888 ipath_dev_err(dd, "PCIe width %u, "
892 ipath_dev_err(dd, "Can't find PCI Express "
897 static void ipath_init_pe_variables(struct ipath_devdata *dd)
903 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
904 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
905 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
906 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
909 dd->ipath_hwe_bitsextant =
929 dd->ipath_i_bitsextant =
935 dd->ipath_e_bitsextant =
953 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
954 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
966 static int ipath_reinit_msi(struct ipath_devdata *dd)
972 if (!dd->ipath_msi_lo) {
973 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
979 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
980 ipath_dev_err(dd, "Can't find MSI capability, "
986 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
987 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
988 dd->ipath_msi_lo);
990 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
991 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
992 dd->ipath_msi_hi);
993 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
999 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1003 pci_write_config_word(dd->pcidev, pos +
1005 dd->ipath_msi_data);
1008 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1009 dd->ipath_pci_cacheline);
1011 pci_set_master(dd->pcidev);
1022 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1029 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1031 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1032 val = dd->ipath_control | INFINIPATH_C_RESET;
1033 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1044 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1045 dd->ipath_pcibar0)))
1046 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1049 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1050 dd->ipath_pcibar1)))
1051 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1054 if ((r = pci_enable_device(dd->pcidev)))
1055 ipath_dev_err(dd, "pci_enable_device failed after "
1058 dd->ipath_flags |= IPATH_PRESENT;
1059 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1060 if (val == dd->ipath_revision) {
1064 ret = ipath_reinit_msi(dd);
1080 * @dd: the infinipath device
1089 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1095 if (pa != dd->ipath_tidinvalid) {
1097 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1104 ipath_dev_err(dd,
1109 pa |= dd->ipath_tidtemplate;
1114 spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1115 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1116 if (dd->ipath_kregbase)
1118 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1120 spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1124 * @dd: the infinipath device
1133 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1138 if (pa != dd->ipath_tidinvalid) {
1140 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1147 ipath_dev_err(dd,
1152 pa |= dd->ipath_tidtemplate;
1156 if (dd->ipath_kregbase)
1164 * @dd: the infinipath device
1172 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1178 if (!dd->ipath_kregbase)
1183 tidinv = dd->ipath_tidinvalid;
1185 ((char __iomem *)(dd->ipath_kregbase) +
1186 dd->ipath_rcvtidbase +
1187 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1189 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1190 ipath_pe_put_tid(dd, &tidbase[i], 0, tidinv);
1193 ((char __iomem *)(dd->ipath_kregbase) +
1194 dd->ipath_rcvegrbase +
1195 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1197 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1198 ipath_pe_put_tid(dd, &tidbase[i], 1, tidinv);
1203 * @dd: the infinipath device
1207 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1209 u32 egrsize = dd->ipath_rcvegrbufsize;
1220 dd->ipath_tidtemplate = 1U << 29;
1222 dd->ipath_tidtemplate = 2U << 29;
1225 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1226 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1228 dd->ipath_tidtemplate = 2U << 29;
1230 dd->ipath_tidinvalid = 0;
1233 static int ipath_pe_early_init(struct ipath_devdata *dd)
1235 dd->ipath_flags |= IPATH_4BYTE_TID;
1245 dd->ipath_rcvhdrentsize = 24;
1246 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1253 dd->ipath_rcvegrbufsize = 2048;
1258 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1259 dd->ipath_rcvegrbufsize +
1260 (dd->ipath_rcvhdrentsize << 2));
1261 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1268 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1270 ipath_get_eeprom_info(dd);
1291 struct ipath_devdata *dd;
1303 dd = pd->port_dd;
1305 if (dd != NULL && dd->ipath_minrev >= 2) {
1317 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1319 free_irq(dd->ipath_irq, dd);
1320 dd->ipath_irq = 0;
1332 static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1340 ipath_dev_err(dd,
1345 dev_info(&dd->pcidev->dev,
1348 ipath_disarm_senderrbufs(dd, 1);
1354 * @dd: the infinipath device
1359 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1361 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1362 dd->ipath_f_bus = ipath_setup_pe_config;
1363 dd->ipath_f_reset = ipath_setup_pe_reset;
1364 dd->ipath_f_get_boardname = ipath_pe_boardname;
1365 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1366 dd->ipath_f_early_init = ipath_pe_early_init;
1367 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1368 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1369 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1370 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1371 if (dd->ipath_minrev >= 2)
1372 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
1374 dd->ipath_f_put_tid = ipath_pe_put_tid;
1375 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1376 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1377 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1378 dd->ipath_f_free_irq = ipath_pe_free_irq;
1381 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1387 dd->ipath_kregs = &ipath_pe_kregs;
1388 dd->ipath_cregs = &ipath_pe_cregs;
1390 ipath_init_pe_variables(dd);