Lines Matching refs:reg_write
226 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
254 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
354 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
400 reg_write(ohci, d->ctrlClear, 0xffffffff);
403 reg_write(ohci, d->ctrlSet, 0xd0000000);
406 reg_write(ohci, d->ctxtMatch, 0xf0000000);
409 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
410 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
413 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx);
417 reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
420 reg_write(ohci, d->ctrlSet, 0x00008000);
442 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx);
454 reg_write(ohci, reg, 0xffffffff);
484 reg_write(ohci, OHCI1394_BusOptions, buf);
487 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
490 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable);
493 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
497 reg_write(ohci, OHCI1394_LinkControlSet,
508 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
511 reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID);
514 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
521 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
522 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
525 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
526 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
540 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
548 reg_write(ohci, OHCI1394_PhyUpperBound,
555 reg_write(ohci, OHCI1394_ATRetries,
561 reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);
564 reg_write(ohci, OHCI1394_IntMaskSet,
580 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
617 reg_write(ohci, OHCI1394_BusOptions,
623 reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000);
631 reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000);
829 reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z);
835 reg_write(ohci, d->ctrlSet, 0x8000);
842 reg_write(ohci, d->ctrlSet, 0x1000);
970 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
986 reg_write(ohci, OHCI1394_LinkControlSet,
992 reg_write(ohci, OHCI1394_LinkControlClear,
1063 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet,
1066 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet,
1100 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear,
1103 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear,
1299 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, 0xFFFFFFFF);
1300 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, 0xFFFFFFFF);
1325 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << recv->task.context);
1413 reg_write(recv->ohci, reg, (1 << i));
1428 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoSet, (1 << i));
1430 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiSet, (1 << (i-32)));
1433 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, (1 << i));
1435 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, (1 << (i-32)));
1450 reg_write(recv->ohci, recv->ContextControlClear, 0xFFFFFFFF);
1459 reg_write(recv->ohci, recv->ContextControlSet, command);
1466 reg_write(recv->ohci, recv->ContextControlSet, (1 << 28));
1476 reg_write(recv->ohci, recv->ContextControlSet, (1 << 29));
1502 reg_write(recv->ohci, recv->ContextMatch, contextMatch);
1509 reg_write(recv->ohci, recv->CommandPtr, command);
1512 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskSet, 1 << recv->task.context);
1517 reg_write(recv->ohci, recv->ContextControlSet, 0x8000);
1570 reg_write(recv->ohci, recv->ContextControlSet, (1 << 12));
1933 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskClear, 1 << xmit->task.context);
2089 reg_write(xmit->ohci, xmit->ContextControlSet, 1 << 12);
2105 reg_write(xmit->ohci, xmit->ContextControlClear, 0xFFFFFFFF);
2109 reg_write(xmit->ohci, xmit->CommandPtr,
2125 reg_write(xmit->ohci, xmit->ContextControlSet, 0x80000000 | (start << 16));
2129 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskSet, 1 << xmit->task.context);
2132 reg_write(xmit->ohci, xmit->ContextControlSet, 0x8000);
2284 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
2357 reg_write(ohci, OHCI1394_LinkControlSet,
2373 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2381 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2458 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, rx_event);
2466 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, tx_event);
2494 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2495 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2503 reg_write(ohci, OHCI1394_PhyReqFilterHiSet,
2505 reg_write(ohci, OHCI1394_PhyReqFilterLoSet,
2554 reg_write(ohci, d->ctrlSet, 0x1000);
2869 reg_write(d->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << d->ctx);
3133 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(config_rom[0]));
3134 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(config_rom[2]));
3146 reg_write(ohci, OHCI1394_CSRData, data);
3147 reg_write(ohci, OHCI1394_CSRCompareData, compare);
3148 reg_write(ohci, OHCI1394_CSRControl, reg & 0x3);
3325 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3328 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3329 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3419 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3420 reg_write(ohci, OHCI1394_BusOptions,
3427 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3428 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3429 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3430 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3431 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3432 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3438 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3515 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3516 reg_write(ohci, OHCI1394_BusOptions,
3519 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3520 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3521 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3522 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3523 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3524 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3526 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3584 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3585 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3586 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3633 reg_write(ohci, reg, 0x8000);