Lines Matching defs:timings
68 u32 timings[4];
145 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
146 * register controls the UDMA timings. At least, it seems bit 0
201 * is used to reach long timings used in this mode.
231 /* Rounded Multiword DMA timings
282 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
296 /* UniNorth 2 ATA/100 timings */
460 * Apply the timings of the proper unit (master/slave) to the shared
473 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
475 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
480 * Apply the timings of the proper unit (master/slave) to the shared
493 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
494 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
496 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
497 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
613 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
619 u32 *timings;
628 timings = &pmif->timings[drive->select.b.unit & 0x01];
638 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
647 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
661 *timings = ((*timings) & ~TR_66_PIO_MASK) |
683 *timings = ((*timings) & ~TR_33_PIO_MASK) |
687 *timings |= TR_33_PIO_E;
694 drive->name, pio, *timings);
704 * Calculate KeyLargo ATA/66 UDMA timings
707 set_timings_udma_ata4(u32 *timings, u8 speed)
718 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
725 speed & 0xf, *timings);
732 * Calculate Kauai ATA/100 UDMA timings
752 * Calculate Shasta ATA/133 UDMA timings
772 * Calculate MDMA timings for all cells
775 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
838 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
847 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
860 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
873 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
897 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
901 *timings |= TR_33_MDMA_HALFTICK;
906 drive->name, speed & 0xf, *timings);
925 u32 *timings, *timings2;
930 timings = &pmif->timings[unit];
931 timings2 = &pmif->timings[unit+2];
951 ret = set_timings_udma_ata4(timings, speed);
954 ret = set_timings_udma_ata6(timings, timings2, speed);
956 ret = set_timings_udma_shasta(timings, timings2, speed);
963 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
1024 pmif->timings[0] = pmif->timings[1] = value;
1025 pmif->timings[2] = pmif->timings[3] = value2;
1087 /* We clear the timings */
1088 pmif->timings[0] = 0;
1089 pmif->timings[1] = 0;
1136 /* Sanitize drive timings */
1204 /* Make sure we have sane timings */
1693 u32 *timings, *timings2;
1698 timings = &pmif->timings[drive->select.b.unit & 0x01];
1699 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1707 /* Copy timings to local image */
1708 timing_local[0] = *timings;
1711 /* Calculate controller timings */
1728 /* Apply timings to controller */
1729 *timings = timing_local[0];
1748 u32 *timings, *timings2;
1753 timings = &pmif->timings[drive->select.b.unit & 0x01];
1754 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1756 /* Copy timings to local image */
1757 timing_local[0] = *timings;
1760 /* Calculate timings for interface */
1783 /* Apply timings to controller */
1784 *timings = timing_local[0];
1848 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1870 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1871 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),