Lines Matching defs:Control
147 volatile u16 status; /* Control/status field */
362 #define CCR 0x06 /* Channel Control Register */
364 #define PCR 0x0a /* Port Control Register */
366 #define TMCR 0x0e /* Test mode Control Register */
367 #define CMCR 0x10 /* Clock mode Control Register */
370 #define IOCR 0x16 /* Input/Output Control Register */
371 #define ICR 0x18 /* Interrupt Control Register */
372 #define DCCR 0x1a /* Daisy Chain Control Register */
374 #define SICR 0x1e /* status Interrupt Control Register */
378 #define RICR 0x26 /* Receive Interrupt Control Register */
386 #define TICR 0x36 /* Transmit Interrupt Control Register */
397 #define DCR 0x06 /* DMA Control Register (shared) */
399 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
401 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
508 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
541 * Transmit Control/status Register (TCSR)
642 * Transmit status Bits in Transmit Control status Register (TCSR)
643 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
671 /* Transmit status Bits in Transmit Control status Register (TCSR) */
672 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
4836 /* Receive Interrupt Control Register (RICR)
4905 /* Transmit Interrupt Control Register (TICR)
5062 /* Channel Control/status Register (CCSR)
5111 /* DMA Control Register (DCR)
5160 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5173 /* DMA Interrupt Control Register (DICR)
5192 /* Channel Control Register (CCR)
5194 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5225 * Burst/Dwell Control Register
5259 /* Clock mode Control Register (CMCR)
5288 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5351 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5808 /* Set BIT30 of Misc Control Register */
5809 /* (Local Control Register 0x50) to force reset of USC. */
5874 /* Port Control Register (PCR)
5892 * Input/Output Control Register
5977 /* Receive Interrupt Control Register (RICR)
6036 /* Transmit Interrupt Control Register (TICR)
6059 /* Channel Control/status Register (CCSR)
6129 /* Channel Control Register (CCR)
6131 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6306 u16 Control;
6309 /* get the current value of the Port Control Register (PCR) */
6311 Control = usc_InReg( info, PCR );
6314 Control &= ~(BIT6);
6316 Control |= BIT6;
6319 Control &= ~(BIT4);
6321 Control |= BIT4;
6323 usc_OutReg( info, PCR, Control );
6340 * Clock mode Control Register (CMCR)
6378 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6415 * DMA. Control information is read from the buffer entries by the