Lines Matching refs:dev_priv
29 void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv,
32 uint32_t scstart = dev_priv->state.s3d.new_scstart;
33 uint32_t scend = dev_priv->state.s3d.new_scend;
40 if (scstart != dev_priv->state.s3d.scstart ||
41 scend != dev_priv->state.s3d.scend) {
48 dev_priv->state.s3d.scstart = scstart;
49 dev_priv->state.s3d.scend = scend;
50 dev_priv->waiting = 1;
55 void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv,
58 uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0;
59 uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1;
66 if (drawctrl0 != dev_priv->state.s4.drawctrl0 ||
67 drawctrl1 != dev_priv->state.s4.drawctrl1) {
74 dev_priv->state.s4.drawctrl0 = drawctrl0;
75 dev_priv->state.s4.drawctrl1 = drawctrl1;
76 dev_priv->waiting = 1;
81 static int savage_verify_texaddr(drm_savage_private_t * dev_priv, int unit,
90 if (addr < dev_priv->texture_offset ||
91 addr >= dev_priv->texture_offset + dev_priv->texture_size) {
98 if (!dev_priv->agp_textures) {
104 if (addr < dev_priv->agp_textures->offset ||
105 addr >= (dev_priv->agp_textures->offset +
106 dev_priv->agp_textures->size)) {
118 dev_priv->state.where = regs[reg - start]
123 dev_priv->state.where = (tmp & (mask)) | \
124 (dev_priv->state.where & ~(mask)); \
128 static int savage_verify_state_s3d(drm_savage_private_t * dev_priv,
150 if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK)
151 return savage_verify_texaddr(dev_priv, 0,
152 dev_priv->state.s3d.texaddr);
158 static int savage_verify_state_s4(drm_savage_private_t * dev_priv,
183 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK)
184 ret |= savage_verify_texaddr(dev_priv, 0,
185 dev_priv->state.s4.texaddr0);
186 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK)
187 ret |= savage_verify_texaddr(dev_priv, 1,
188 dev_priv->state.s4.texaddr1);
197 static int savage_dispatch_state(drm_savage_private_t * dev_priv,
211 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
212 ret = savage_verify_state_s3d(dev_priv, start, count, regs);
229 ret = savage_verify_state_s4(dev_priv, start, count, regs);
253 dev_priv->waiting = 1;
278 static int savage_dispatch_dma_prim(drm_savage_private_t * dev_priv,
323 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
353 if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {
356 BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);
357 dev_priv->state.common.vbaddr = dmabuf->bus_address;
359 if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {
363 dev_priv->waiting = 0;
386 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
413 static int savage_dispatch_vb_prim(drm_savage_private_t * dev_priv,
455 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
531 static int savage_dispatch_dma_idx(drm_savage_private_t * dev_priv,
574 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
598 if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {
601 BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);
602 dev_priv->state.common.vbaddr = dmabuf->bus_address;
604 if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {
608 dev_priv->waiting = 0;
640 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
667 static int savage_dispatch_vb_idx(drm_savage_private_t * dev_priv,
707 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
781 static int savage_dispatch_clear(drm_savage_private_t * dev_priv,
824 DMA_WRITE(dev_priv->front_offset);
825 DMA_WRITE(dev_priv->front_bd);
828 DMA_WRITE(dev_priv->back_offset);
829 DMA_WRITE(dev_priv->back_bd);
832 DMA_WRITE(dev_priv->depth_offset);
833 DMA_WRITE(dev_priv->depth_bd);
853 static int savage_dispatch_swap(drm_savage_private_t * dev_priv,
870 DMA_WRITE(dev_priv->back_offset);
871 DMA_WRITE(dev_priv->back_bd);
882 static int savage_dispatch_draw(drm_savage_private_t * dev_priv,
896 dev_priv->emit_clip_rect(dev_priv, &boxes[i]);
906 dev_priv, &cmd_header, dmabuf);
910 dev_priv, &cmd_header,
916 ret = savage_dispatch_dma_idx(dev_priv,
924 ret = savage_dispatch_vb_idx(dev_priv,
949 drm_savage_private_t *dev_priv = dev->dev_private;
1033 dev_priv->waiting = 1;
1067 dev_priv, first_draw_cmd,
1090 ret = savage_dispatch_state(dev_priv, &cmd_header,
1103 ret = savage_dispatch_clear(dev_priv, &cmd_header,
1110 ret = savage_dispatch_swap(dev_priv, cmdbuf.nbox,
1128 dev_priv, first_draw_cmd, cmdbuf.cmd_addr, dmabuf,
1142 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
1143 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);