Lines Matching refs:dev_priv
821 drm_radeon_private_t *dev_priv = dev->dev_private;
827 static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
833 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
843 static void radeon_status(drm_radeon_private_t * dev_priv)
869 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
874 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
880 for (i = 0; i < dev_priv->usec_timeout; i++) {
890 radeon_status(dev_priv);
895 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
899 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
901 for (i = 0; i < dev_priv->usec_timeout; i++) {
911 radeon_status(dev_priv);
916 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
920 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
922 ret = radeon_do_wait_for_fifo(dev_priv, 64);
926 for (i = 0; i < dev_priv->usec_timeout; i++) {
929 radeon_do_pixcache_flush(dev_priv);
937 radeon_status(dev_priv);
947 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
952 radeon_do_wait_for_idle(dev_priv);
956 if (dev_priv->microcode_version == UCODE_R200) {
964 } else if (dev_priv->microcode_version == UCODE_R300) {
986 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
993 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1007 return radeon_do_wait_for_idle(dev_priv);
1012 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1017 radeon_do_wait_for_idle(dev_priv);
1019 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1021 dev_priv->cp_running = 1;
1037 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1044 SET_RING_HEAD(dev_priv, cur_read_ptr);
1045 dev_priv->ring.tail = cur_read_ptr;
1052 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1058 dev_priv->cp_running = 0;
1065 drm_radeon_private_t *dev_priv = dev->dev_private;
1069 radeon_do_pixcache_flush(dev_priv);
1108 radeon_do_cp_reset(dev_priv);
1111 dev_priv->cp_running = 0;
1120 drm_radeon_private_t * dev_priv)
1130 if (!dev_priv->new_memmap)
1132 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1133 | (dev_priv->fb_location >> 16));
1136 if (dev_priv->flags & RADEON_IS_AGP) {
1139 (((dev_priv->gart_vm_start - 1 +
1140 dev_priv->gart_size) & 0xffff0000) |
1141 (dev_priv->gart_vm_start >> 16)));
1143 ring_start = (dev_priv->cp_ring->offset
1145 + dev_priv->gart_vm_start);
1148 ring_start = (dev_priv->cp_ring->offset
1150 + dev_priv->gart_vm_start);
1160 SET_RING_HEAD(dev_priv, cur_read_ptr);
1161 dev_priv->ring.tail = cur_read_ptr;
1164 if (dev_priv->flags & RADEON_IS_AGP) {
1166 dev_priv->ring_rptr->offset
1167 - dev->agp->base + dev_priv->gart_vm_start);
1174 tmp_ofs = dev_priv->ring_rptr->offset -
1187 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1189 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1193 dev_priv->writeback_works = 0;
1205 dev_priv->scratch = ((__volatile__ u32 *)
1206 dev_priv->ring_rptr->handle +
1215 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1216 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1218 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1220 dev_priv->sarea_priv->last_dispatch);
1222 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1223 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1225 radeon_do_wait_for_idle(dev_priv);
1236 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1243 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1246 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1247 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1253 if (tmp < dev_priv->usec_timeout) {
1254 dev_priv->writeback_works = 1;
1257 dev_priv->writeback_works = 0;
1261 dev_priv->writeback_works = 0;
1265 if (!dev_priv->writeback_works) {
1274 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1281 dev_priv->gart_vm_start,
1282 (long)dev_priv->gart_info.bus_addr,
1283 dev_priv->gart_size);
1289 dev_priv->gart_info.bus_addr);
1291 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1294 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1295 dev_priv->gart_size = 32*1024*1024;
1297 (((dev_priv->gart_vm_start - 1 +
1298 dev_priv->gart_size) & 0xffff0000) |
1299 (dev_priv->gart_vm_start >> 16)));
1301 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1304 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1306 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1311 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1313 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1317 dev_priv->gart_vm_start,
1318 (long)dev_priv->gart_info.bus_addr,
1319 dev_priv->gart_size);
1321 dev_priv->gart_vm_start);
1323 dev_priv->gart_info.bus_addr);
1325 dev_priv->gart_vm_start);
1327 dev_priv->gart_vm_start +
1328 dev_priv->gart_size - 1);
1341 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1345 if (dev_priv->flags & RADEON_IS_IGPGART) {
1346 radeon_set_igpgart(dev_priv, on);
1350 if (dev_priv->flags & RADEON_IS_PCIE) {
1351 radeon_set_pciegart(dev_priv, on);
1363 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1367 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1368 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1369 + dev_priv->gart_size - 1);
1383 drm_radeon_private_t *dev_priv = dev->dev_private;
1388 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1394 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1396 dev_priv->flags &= ~RADEON_IS_AGP;
1397 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1400 dev_priv->flags |= RADEON_IS_AGP;
1403 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1409 dev_priv->usec_timeout = init->usec_timeout;
1410 if (dev_priv->usec_timeout < 1 ||
1411 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1419 dev_priv->microcode_version = UCODE_R200;
1422 dev_priv->microcode_version = UCODE_R300;
1425 dev_priv->microcode_version = UCODE_R100;
1428 dev_priv->do_boxes = 0;
1429 dev_priv->cp_mode = init->cp_mode;
1444 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1448 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1451 dev_priv->front_offset = init->front_offset;
1452 dev_priv->front_pitch = init->front_pitch;
1453 dev_priv->back_offset = init->back_offset;
1454 dev_priv->back_pitch = init->back_pitch;
1458 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1462 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1465 dev_priv->depth_offset = init->depth_offset;
1466 dev_priv->depth_pitch = init->depth_pitch;
1473 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1474 (dev_priv->color_fmt << 10) |
1475 (dev_priv->microcode_version ==
1478 dev_priv->depth_clear.rb3d_zstencilcntl =
1479 (dev_priv->depth_fmt |
1486 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1500 dev_priv->ring_offset = init->ring_offset;
1501 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1502 dev_priv->buffers_offset = init->buffers_offset;
1503 dev_priv->gart_textures_offset = init->gart_textures_offset;
1505 if (!dev_priv->sarea) {
1511 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1512 if (!dev_priv->cp_ring) {
1517 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1518 if (!dev_priv->ring_rptr) {
1532 dev_priv->gart_textures =
1534 if (!dev_priv->gart_textures) {
1541 dev_priv->sarea_priv =
1542 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1546 if (dev_priv->flags & RADEON_IS_AGP) {
1547 drm_core_ioremap(dev_priv->cp_ring, dev);
1548 drm_core_ioremap(dev_priv->ring_rptr, dev);
1550 if (!dev_priv->cp_ring->handle ||
1551 !dev_priv->ring_rptr->handle ||
1560 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1561 dev_priv->ring_rptr->handle =
1562 (void *)dev_priv->ring_rptr->offset;
1566 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1567 dev_priv->cp_ring->handle);
1568 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1569 dev_priv->ring_rptr->handle);
1574 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1576 dev_priv->fb_size =
1578 - dev_priv->fb_location;
1580 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1581 ((dev_priv->front_offset
1582 + dev_priv->fb_location) >> 10));
1584 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1585 ((dev_priv->back_offset
1586 + dev_priv->fb_location) >> 10));
1588 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1589 ((dev_priv->depth_offset
1590 + dev_priv->fb_location) >> 10));
1592 dev_priv->gart_size = init->gart_size;
1595 if (dev_priv->new_memmap) {
1605 if (dev_priv->flags & RADEON_IS_AGP) {
1608 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1609 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1618 base = dev_priv->fb_location + dev_priv->fb_size;
1619 if (base < dev_priv->fb_location ||
1620 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1621 base = dev_priv->fb_location
1622 - dev_priv->gart_size;
1624 dev_priv->gart_vm_start = base & 0xffc00000u;
1625 if (dev_priv->gart_vm_start != base)
1627 base, dev_priv->gart_vm_start);
1630 dev_priv->gart_vm_start = dev_priv->fb_location +
1635 if (dev_priv->flags & RADEON_IS_AGP)
1636 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1638 + dev_priv->gart_vm_start);
1641 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1643 + dev_priv->gart_vm_start);
1645 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1646 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1647 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1648 dev_priv->gart_buffers_offset);
1650 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1651 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1653 dev_priv->ring.size = init->ring_size;
1654 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1656 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1658 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1661 if (dev_priv->flags & RADEON_IS_AGP) {
1663 radeon_set_pcigart(dev_priv, 0);
1668 if (dev_priv->pcigart_offset_set) {
1669 dev_priv->gart_info.bus_addr =
1670 dev_priv->pcigart_offset + dev_priv->fb_location;
1671 dev_priv->gart_info.mapping.offset =
1672 dev_priv->gart_info.bus_addr;
1673 dev_priv->gart_info.mapping.size =
1674 dev_priv->gart_info.table_size;
1676 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1677 dev_priv->gart_info.addr =
1678 dev_priv->gart_info.mapping.handle;
1680 if (dev_priv->flags & RADEON_IS_PCIE)
1681 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1683 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1684 dev_priv->gart_info.gart_table_location =
1688 dev_priv->gart_info.addr,
1689 dev_priv->pcigart_offset);
1691 if (dev_priv->flags & RADEON_IS_IGPGART)
1692 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1694 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1695 dev_priv->gart_info.gart_table_location =
1697 dev_priv->gart_info.addr = NULL;
1698 dev_priv->gart_info.bus_addr = 0;
1699 if (dev_priv->flags & RADEON_IS_PCIE) {
1707 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1714 radeon_set_pcigart(dev_priv, 1);
1717 radeon_cp_load_microcode(dev_priv);
1718 radeon_cp_init_ring_buffer(dev, dev_priv);
1720 dev_priv->last_buf = 0;
1723 radeon_test_writeback(dev_priv);
1730 drm_radeon_private_t *dev_priv = dev->dev_private;
1741 if (dev_priv->flags & RADEON_IS_AGP) {
1742 if (dev_priv->cp_ring != NULL) {
1743 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1744 dev_priv->cp_ring = NULL;
1746 if (dev_priv->ring_rptr != NULL) {
1747 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1748 dev_priv->ring_rptr = NULL;
1758 if (dev_priv->gart_info.bus_addr) {
1760 radeon_set_pcigart(dev_priv, 0);
1761 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1765 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1767 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1768 dev_priv->gart_info.addr = 0;
1772 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1786 drm_radeon_private_t *dev_priv = dev->dev_private;
1788 if (!dev_priv) {
1796 if (dev_priv->flags & RADEON_IS_AGP) {
1798 radeon_set_pcigart(dev_priv, 0);
1803 radeon_set_pcigart(dev_priv, 1);
1806 radeon_cp_load_microcode(dev_priv);
1807 radeon_cp_init_ring_buffer(dev, dev_priv);
1844 drm_radeon_private_t *dev_priv = dev->dev_private;
1849 if (dev_priv->cp_running) {
1853 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1855 __FUNCTION__, dev_priv->cp_mode);
1859 radeon_do_cp_start(dev_priv);
1870 drm_radeon_private_t *dev_priv = dev->dev_private;
1880 if (!dev_priv->cp_running)
1887 radeon_do_cp_flush(dev_priv);
1894 ret = radeon_do_cp_idle(dev_priv);
1903 radeon_do_cp_stop(dev_priv);
1913 drm_radeon_private_t *dev_priv = dev->dev_private;
1916 if (dev_priv) {
1917 if (dev_priv->cp_running) {
1919 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1927 radeon_do_cp_stop(dev_priv);
1932 if (dev_priv->mmio) /* remove this after permanent addmaps */
1935 if (dev_priv->mmio) { /* remove all surfaces */
1946 radeon_mem_takedown(&(dev_priv->gart_heap));
1947 radeon_mem_takedown(&(dev_priv->fb_heap));
1959 drm_radeon_private_t *dev_priv = dev->dev_private;
1964 if (!dev_priv) {
1969 radeon_do_cp_reset(dev_priv);
1972 dev_priv->cp_running = 0;
1980 drm_radeon_private_t *dev_priv = dev->dev_private;
1985 return radeon_do_cp_idle(dev_priv);
2026 drm_radeon_private_t *dev_priv = dev->dev_private;
2032 if (++dev_priv->last_buf >= dma->buf_count)
2033 dev_priv->last_buf = 0;
2035 start = dev_priv->last_buf;
2037 for (t = 0; t < dev_priv->usec_timeout; t++) {
2045 dev_priv->stats.requested_bufs++;
2054 dev_priv->stats.freelist_loops++;
2066 drm_radeon_private_t *dev_priv = dev->dev_private;
2069 dev_priv->last_buf = 0;
2081 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
2083 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2085 u32 last_head = GET_RING_HEAD(dev_priv);
2087 for (i = 0; i < dev_priv->usec_timeout; i++) {
2088 u32 head = GET_RING_HEAD(dev_priv);
2096 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2106 radeon_status(dev_priv);
2178 drm_radeon_private_t *dev_priv;
2181 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2182 if (dev_priv == NULL)
2185 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2186 dev->dev_private = (void *)dev_priv;
2187 dev_priv->flags = flags;
2197 dev_priv->flags |= RADEON_HAS_HIERZ;
2205 dev_priv->flags |= RADEON_IS_AGP;
2207 dev_priv->flags |= RADEON_IS_PCIE;
2209 dev_priv->flags |= RADEON_IS_PCI;
2212 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2223 drm_radeon_private_t *dev_priv = dev->dev_private;
2225 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2229 _DRM_READ_ONLY, &dev_priv->mmio);
2244 drm_radeon_private_t *dev_priv = dev->dev_private;
2247 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);