Lines Matching refs:dev_priv
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
65 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
78 drm_i915_private_t *dev_priv = dev->dev_private;
79 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
88 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
101 drm_i915_private_t *dev_priv =
104 if (dev_priv->ring.virtual_start) {
105 drm_core_ioremapfree(&dev_priv->ring.map, dev);
108 if (dev_priv->status_page_dmah) {
109 drm_pci_free(dev, dev_priv->status_page_dmah);
114 if (dev_priv->status_gfx_addr) {
115 dev_priv->status_gfx_addr = 0;
116 drm_core_ioremapfree(&dev_priv->hws_map, dev);
130 drm_i915_private_t * dev_priv,
133 memset(dev_priv, 0, sizeof(drm_i915_private_t));
136 if (!dev_priv->sarea) {
138 dev->dev_private = (void *)dev_priv;
143 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
144 if (!dev_priv->mmio_map) {
145 dev->dev_private = (void *)dev_priv;
151 dev_priv->sarea_priv = (drm_i915_sarea_t *)
152 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
154 dev_priv->ring.Start = init->ring_start;
155 dev_priv->ring.End = init->ring_end;
156 dev_priv->ring.Size = init->ring_size;
157 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
159 dev_priv->ring.map.offset = init->ring_start;
160 dev_priv->ring.map.size = init->ring_size;
161 dev_priv->ring.map.type = 0;
162 dev_priv->ring.map.flags = 0;
163 dev_priv->ring.map.mtrr = 0;
165 drm_core_ioremap(&dev_priv->ring.map, dev);
167 if (dev_priv->ring.map.handle == NULL) {
168 dev->dev_private = (void *)dev_priv;
175 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
177 dev_priv->cpp = init->cpp;
178 dev_priv->back_offset = init->back_offset;
179 dev_priv->front_offset = init->front_offset;
180 dev_priv->current_page = 0;
181 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
186 dev_priv->use_mi_batchbuffer_start = 0;
190 dev_priv->allow_batchbuffer = 1;
194 dev_priv->status_page_dmah =
197 if (!dev_priv->status_page_dmah) {
198 dev->dev_private = (void *)dev_priv;
203 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
204 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
206 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
207 I915_WRITE(0x02080, dev_priv->dma_status_page);
210 dev->dev_private = (void *)dev_priv;
216 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
220 if (!dev_priv->sarea) {
225 if (!dev_priv->mmio_map) {
230 if (dev_priv->ring.map.handle == NULL) {
237 if (!dev_priv->hw_status_page) {
241 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
243 if (dev_priv->status_gfx_addr != 0)
244 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
246 I915_WRITE(0x02080, dev_priv->dma_status_page);
255 drm_i915_private_t *dev_priv;
264 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
266 if (dev_priv == NULL)
268 retcode = i915_initialize(dev, dev_priv, &init);
362 drm_i915_private_t *dev_priv = dev->dev_private;
366 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
403 drm_i915_private_t *dev_priv = dev->dev_private;
441 drm_i915_private_t *dev_priv = dev->dev_private;
444 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
446 if (dev_priv->counter > 0x7FFFFFFFUL)
447 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
452 OUT_RING(dev_priv->counter);
492 drm_i915_private_t *dev_priv = dev->dev_private;
515 if (dev_priv->use_mi_batchbuffer_start) {
537 drm_i915_private_t *dev_priv = dev->dev_private;
542 dev_priv->current_page,
543 dev_priv->sarea_priv->pf_current_page);
555 if (dev_priv->current_page == 0) {
556 OUT_RING(dev_priv->back_offset);
557 dev_priv->current_page = 1;
559 OUT_RING(dev_priv->front_offset);
560 dev_priv->current_page = 0;
570 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
575 OUT_RING(dev_priv->counter);
579 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
585 drm_i915_private_t *dev_priv = dev->dev_private;
588 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
603 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
604 u32 *hw_status = dev_priv->hw_status_page;
606 dev_priv->sarea_priv;
610 if (!dev_priv->allow_batchbuffer) {
637 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
638 u32 *hw_status = dev_priv->hw_status_page;
640 dev_priv->sarea_priv;
684 drm_i915_private_t *dev_priv = dev->dev_private;
688 if (!dev_priv) {
701 value = dev_priv->allow_batchbuffer ? 1 : 0;
704 value = READ_BREADCRUMB(dev_priv);
722 drm_i915_private_t *dev_priv = dev->dev_private;
725 if (!dev_priv) {
735 dev_priv->use_mi_batchbuffer_start = param.value;
738 dev_priv->tex_lru_log_granularity = param.value;
741 dev_priv->allow_batchbuffer = param.value;
754 drm_i915_private_t *dev_priv = dev->dev_private;
757 if (!dev_priv) {
765 dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12);
767 dev_priv->hws_map.offset = dev->agp->agp_info.aper_base + hws.addr;
768 dev_priv->hws_map.size = 4*1024;
769 dev_priv->hws_map.type = 0;
770 dev_priv->hws_map.flags = 0;
771 dev_priv->hws_map.mtrr = 0;
773 drm_core_ioremap(&dev_priv->hws_map, dev);
774 if (dev_priv->hws_map.handle == NULL) {
775 dev->dev_private = (void *)dev_priv;
777 dev_priv->status_gfx_addr = 0;
782 dev_priv->hw_status_page = dev_priv->hws_map.handle;
784 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
785 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
787 dev_priv->status_gfx_addr);
788 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
807 drm_i915_private_t *dev_priv = dev->dev_private;
808 i915_mem_takedown(&(dev_priv->agp_heap));
816 drm_i915_private_t *dev_priv = dev->dev_private;
817 i915_mem_release(dev, filp, dev_priv->agp_heap);