Lines Matching defs:sarea_priv
277 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
296 dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY;
373 dev_priv->sarea_priv = (drm_i830_sarea_t *)
699 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
700 unsigned int dirty = sarea_priv->dirty;
705 i830EmitDestVerified(dev, sarea_priv->BufferState);
706 sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS;
710 i830EmitContextVerified(dev, sarea_priv->ContextState);
711 sarea_priv->dirty &= ~I830_UPLOAD_CTX;
715 i830EmitTexVerified(dev, sarea_priv->TexState[0]);
716 sarea_priv->dirty &= ~I830_UPLOAD_TEX0;
720 i830EmitTexVerified(dev, sarea_priv->TexState[1]);
721 sarea_priv->dirty &= ~I830_UPLOAD_TEX1;
725 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[0],
726 sarea_priv->TexBlendStateWordsUsed[0]);
727 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0;
731 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[1],
732 sarea_priv->TexBlendStateWordsUsed[1]);
733 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1;
737 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 1);
740 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 0);
741 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(0);
744 i830EmitTexPalette(dev, sarea_priv->Palette[1], 1, 0);
745 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(1);
755 i830EmitStippleVerified(dev, sarea_priv->StippleState);
756 sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE;
760 i830EmitTexVerified(dev, sarea_priv->TexState2);
761 sarea_priv->dirty &= ~I830_UPLOAD_TEX2;
765 i830EmitTexVerified(dev, sarea_priv->TexState3);
766 sarea_priv->dirty &= ~I830_UPLOAD_TEX3;
771 sarea_priv->TexBlendState2,
772 sarea_priv->TexBlendStateWordsUsed2);
774 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2;
779 sarea_priv->TexBlendState3,
780 sarea_priv->TexBlendStateWordsUsed3);
781 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3;
799 x += dev_priv->sarea_priv->boxes[0].x1;
800 y += dev_priv->sarea_priv->boxes[0].y1;
833 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP)
838 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT)
843 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT)
848 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD)
853 if (!(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY))
869 dev_priv->sarea_priv->perf_boxes = 0;
878 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
879 int nbox = sarea_priv->nbox;
880 drm_clip_rect_t *pbox = sarea_priv->boxes;
970 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
971 int nbox = sarea_priv->nbox;
972 drm_clip_rect_t *pbox = sarea_priv->boxes;
1045 dev_priv->sarea_priv->pf_current_page);
1050 dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP;
1077 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1085 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
1086 drm_clip_rect_t *box = sarea_priv->boxes;
1087 int nbox = sarea_priv->nbox;
1109 if (sarea_priv->dirty)
1126 sarea_priv->vertex_prim | ((used / 4) - 2));
1146 OUT_RING(sarea_priv->
1150 OUT_RING(sarea_priv->
1292 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1293 dev_priv->sarea_priv;
1312 sarea_priv->last_enqueue = dev_priv->counter - 1;
1313 sarea_priv->last_dispatch = (int)hw_status[5];
1365 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1405 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1406 dev_priv->sarea_priv;
1408 sarea_priv->last_dispatch = (int)hw_status[5];
1421 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1422 dev_priv->sarea_priv;
1439 sarea_priv->last_dispatch = (int)hw_status[5];