Lines Matching refs:registers
49 /* Intel i820 registers */
53 /* Intel i840 registers */
57 /* Intel i850 registers */
61 /* intel 915G registers */
70 /* Intel 965G registers */
73 /* Intel 7505 registers */
104 u8 __iomem *registers;
150 if (!intel_private.registers) {
154 intel_private.registers = ioremap(temp, 128 * 4096);
155 if (!intel_private.registers) {
161 if ((readl(intel_private.registers+I810_DRAM_CTL)
169 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
170 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
174 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
175 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
184 writel(0, intel_private.registers+I810_PGETBL_CTL);
185 readl(intel_private.registers); /* PCI Posting. */
186 iounmap(intel_private.registers);
284 intel_private.registers+I810_PTE_BASE+(i*4));
286 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
296 intel_private.registers+I810_PTE_BASE+(j*4));
298 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
321 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
323 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
440 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
498 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
592 intel_private.registers = ioremap(temp,128 * 4096);
593 if (!intel_private.registers)
596 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
663 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
664 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
668 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
669 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
679 iounmap(intel_private.registers);
725 intel_private.registers+I810_PTE_BASE+(j*4));
727 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
751 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
753 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
784 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
785 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
801 iounmap(intel_private.registers);
883 * described in the spec of the MSAC registers is just changing of the
929 intel_private.registers = ioremap(temp,128 * 4096);
930 if (!intel_private.registers)
933 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
989 intel_private.registers = ioremap(temp,128 * 4096);
990 if (!intel_private.registers)
993 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;