Lines Matching refs:u32
139 u32 maddr;
212 u32 pcr;
213 u32 saved_tx_quota;
283 u32 sys_pkt_addr;
284 u32 local_pkt_addr;
285 u32 bytes;
810 u32 class_type; /* CBR/VBR/ABR/UBR; use the enum above */
811 u32 pcr; /* Peak Cell Rate (24-bit) */
813 u32 scr; /* sustainable cell rate */
814 u32 max_burst_size; /* ?? cell rate or data rate */
817 u32 mcr; /* Min Cell Rate (24-bit) */
818 u32 icr; /* Initial Cell Rate (24-bit) */
819 u32 tbe; /* Transient Buffer Exposure (24-bit) */
820 u32 frtt; /* Fixed Round Trip Time (24-bit) */
855 u32 fdq_st; /* Free desc queue start address */
856 u32 fdq_ed; /* Free desc queue end address */
857 u32 fdq_rd; /* Free desc queue read pointer */
858 u32 fdq_wr; /* Free desc queue write pointer */
859 u32 pcq_st; /* Packet Complete queue start address */
860 u32 pcq_ed; /* Packet Complete queue end address */
861 u32 pcq_rd; /* Packet Complete queue read pointer */
862 u32 pcq_wr; /* Packet Complete queue write pointer */
866 u32 prq_st; /* Packet Ready Queue Start Address */
867 u32 prq_ed; /* Packet Ready Queue End Address */
868 u32 prq_wr; /* Packet Ready Queue write pointer */
869 u32 tcq_st; /* Transmit Complete Queue Start Address*/
870 u32 tcq_ed; /* Transmit Complete Queue End Address */
871 u32 tcq_rd; /* Transmit Complete Queue read pointer */
875 u32 timestamp;
887 u32 suni_master_reset; /* SUNI Master Reset and Identity */
888 u32 suni_master_config; /* SUNI Master Configuration */
889 u32 suni_master_intr_stat; /* SUNI Master Interrupt Status */
890 u32 suni_reserved1; /* Reserved */
891 u32 suni_master_clk_monitor;/* SUNI Master Clock Monitor */
892 u32 suni_master_control; /* SUNI Master Clock Monitor */
893 u32 suni_reserved2[10]; /* Reserved */
895 u32 suni_rsop_control; /* RSOP Control/Interrupt Enable */
896 u32 suni_rsop_status; /* RSOP Status/Interrupt States */
897 u32 suni_rsop_section_bip8l;/* RSOP Section BIP-8 LSB */
898 u32 suni_rsop_section_bip8m;/* RSOP Section BIP-8 MSB */
900 u32 suni_tsop_control; /* TSOP Control */
901 u32 suni_tsop_diag; /* TSOP Disgnostics */
902 u32 suni_tsop_reserved[2]; /* TSOP Reserved */
904 u32 suni_rlop_cs; /* RLOP Control/Status */
905 u32 suni_rlop_intr; /* RLOP Interrupt Enable/Status */
906 u32 suni_rlop_line_bip24l; /* RLOP Line BIP-24 LSB */
907 u32 suni_rlop_line_bip24; /* RLOP Line BIP-24 */
908 u32 suni_rlop_line_bip24m; /* RLOP Line BIP-24 MSB */
909 u32 suni_rlop_line_febel; /* RLOP Line FEBE LSB */
910 u32 suni_rlop_line_febe; /* RLOP Line FEBE */
911 u32 suni_rlop_line_febem; /* RLOP Line FEBE MSB */
913 u32 suni_tlop_control; /* TLOP Control */
914 u32 suni_tlop_disg; /* TLOP Disgnostics */
915 u32 suni_tlop_reserved[14]; /* TLOP Reserved */
917 u32 suni_rpop_cs; /* RPOP Status/Control */
918 u32 suni_rpop_intr; /* RPOP Interrupt/Status */
919 u32 suni_rpop_reserved; /* RPOP Reserved */
920 u32 suni_rpop_intr_ena; /* RPOP Interrupt Enable */
921 u32 suni_rpop_reserved1[3]; /* RPOP Reserved */
922 u32 suni_rpop_path_sig; /* RPOP Path Signal Label */
923 u32 suni_rpop_bip8l; /* RPOP Path BIP-8 LSB */
924 u32 suni_rpop_bip8m; /* RPOP Path BIP-8 MSB */
925 u32 suni_rpop_febel; /* RPOP Path FEBE LSB */
926 u32 suni_rpop_febem; /* RPOP Path FEBE MSB */
927 u32 suni_rpop_reserved2[4]; /* RPOP Reserved */
929 u32 suni_tpop_cntrl_daig; /* TPOP Control/Disgnostics */
930 u32 suni_tpop_pointer_ctrl; /* TPOP Pointer Control */
931 u32 suni_tpop_sourcer_ctrl; /* TPOP Source Control */
932 u32 suni_tpop_reserved1[2]; /* TPOP Reserved */
933 u32 suni_tpop_arb_prtl; /* TPOP Arbitrary Pointer LSB */
934 u32 suni_tpop_arb_prtm; /* TPOP Arbitrary Pointer MSB */
935 u32 suni_tpop_reserved2; /* TPOP Reserved */
936 u32 suni_tpop_path_sig; /* TPOP Path Signal Lable */
937 u32 suni_tpop_path_status; /* TPOP Path Status */
938 u32 suni_tpop_reserved3[6]; /* TPOP Reserved */
940 u32 suni_racp_cs; /* RACP Control/Status */
941 u32 suni_racp_intr; /* RACP Interrupt Enable/Status */
942 u32 suni_racp_hdr_pattern; /* RACP Match Header Pattern */
943 u32 suni_racp_hdr_mask; /* RACP Match Header Mask */
944 u32 suni_racp_corr_hcs; /* RACP Correctable HCS Error Count */
945 u32 suni_racp_uncorr_hcs; /* RACP Uncorrectable HCS Error Count */
946 u32 suni_racp_reserved[10]; /* RACP Reserved */
948 u32 suni_tacp_control; /* TACP Control */
949 u32 suni_tacp_idle_hdr_pat; /* TACP Idle Cell Header Pattern */
950 u32 suni_tacp_idle_pay_pay; /* TACP Idle Cell Payld Octet Pattern */
951 u32 suni_tacp_reserved[5]; /* TACP Reserved */
953 u32 suni_reserved3[24]; /* Reserved */
955 u32 suni_master_test; /* SUNI Master Test */
956 u32 suni_reserved_test; /* SUNI Reserved for Test */
962 u32 valid; // 1 = oc3 PHY card
963 u32 carrier_detect; // GPIN input
968 u32 rsop_los_count; // loss of signal count
969 u32 rsop_bse_count; // section BIP-8 error count
973 u32 rlop_lbe_count; // BIP-24 count
974 u32 rlop_febe_count; // FEBE count;
979 u32 rpop_bip_count; // path BIP-8 error count
980 u32 rpop_febe_count; // path FEBE error count
984 u32 racp_fu_count; // FIFO underrun count
985 u32 racp_fo_count; // FIFO overrun count
986 u32 racp_chcs_count; // correctable HCS error count
987 u32 racp_uchcs_count; // uncorrectable HCS error count
992 u32 __iomem *phy; /* base pointer into phy(SUNI) */
993 u32 __iomem *dma; /* base pointer into DMA control
995 u32 __iomem *reg; /* base pointer to SAR registers
997 u32 __iomem *seg_reg; /* base pointer to segmentation engine
999 u32 __iomem *reass_reg; /* base pointer to reassemble engine
1001 u32 __iomem *ram; /* base pointer to SAR RAM */
1009 u32 close_pending;
1014 u32 tx_cell_cnt, tx_pkt_cnt;
1022 u32 rx_pkt_ram, rx_tmp_cnt, rx_tmp_jif;
1024 u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
1378 u32 t; \
1392 u32 t; \
1449 u32 _t; \