Lines Matching defs:mmio
365 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
367 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
369 void __iomem *mmio);
370 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
372 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
373 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
397 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
399 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
401 void __iomem *mmio);
402 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
404 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
405 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
407 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
409 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
411 void __iomem *mmio);
412 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
414 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
415 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
416 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1369 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1370 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1470 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1474 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1497 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1498 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1499 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1505 readl(mmio + PCI_IRQ_CAUSE_OFS));
1508 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1510 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1518 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1520 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1545 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1546 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1557 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1558 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1565 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1575 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1577 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1580 mv_reset_pci_bus(pdev, mmio);
1583 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1585 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1589 void __iomem *mmio)
1591 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1600 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1604 writel(0, mmio + MV_GPIO_PORT_CTL);
1607 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1609 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1612 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1615 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1641 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1644 void __iomem *port_mmio = mv_port_base(mmio, port);
1648 mv_channel_reset(hpriv, mmio, port);
1667 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1670 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1685 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1692 mv5_reset_hc_port(hpriv, mmio,
1695 mv5_reset_one_hc(hpriv, mmio, hc);
1702 #define ZERO(reg) writel(0, mmio + (reg))
1703 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1707 tmp = readl(mmio + MV_PCI_MODE);
1709 writel(tmp, mmio + MV_PCI_MODE);
1713 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1725 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1729 mv5_reset_flash(hpriv, mmio);
1731 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1734 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1739 * @mmio: base address of the HBA
1746 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1749 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1803 void __iomem *mmio)
1808 tmp = readl(mmio + MV_RESET_CFG);
1815 port_mmio = mv_port_base(mmio, idx);
1822 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1824 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1827 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1830 void __iomem *port_mmio = mv_port_base(mmio, port);
1893 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1896 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1914 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1923 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1927 mv_channel_reset(hpriv, mmio, ap->port_no);
1962 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
2054 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
2060 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
2064 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
2083 * Initialize shadow register mmio addresses, clear outstanding
2241 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
2245 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2254 hpriv->ops->read_preamp(hpriv, port, mmio);
2256 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2260 hpriv->ops->reset_flash(hpriv, mmio);
2261 hpriv->ops->reset_bus(pdev, mmio);
2262 hpriv->ops->enable_leds(hpriv, mmio);
2266 void __iomem *port_mmio = mv_port_base(mmio, port);
2274 hpriv->ops->phy_errata(hpriv, mmio, port);
2278 void __iomem *port_mmio = mv_port_base(mmio, port);
2283 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2295 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2298 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2301 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
2303 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2307 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2308 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2309 readl(mmio + PCI_IRQ_CAUSE_OFS),
2310 readl(mmio + PCI_IRQ_MASK_OFS));