Lines Matching refs:mmio_base
554 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
560 bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0xffff;
561 bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
565 bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0xffff;
566 bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
597 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
616 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
656 writew(pll_ctl, mmio_base + PDC_PLL_CTL);
657 readw(mmio_base + PDC_PLL_CTL); /* flush */
667 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
683 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
694 scr = readl(mmio_base + PDC_SYS_CTL);
696 writel(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
697 readl(mmio_base + PDC_SYS_CTL); /* flush */
707 scr = readl(mmio_base + PDC_SYS_CTL);
709 writel(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
710 readl(mmio_base + PDC_SYS_CTL); /* flush */
792 void __iomem *mmio_base;
821 mmio_base = host->iomap[PDC_MMIO_BAR];
823 pdc_ata_setup_port(&host->ports[0]->ioaddr, mmio_base + 0x17c0);
824 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x1000;
825 pdc_ata_setup_port(&host->ports[1]->ioaddr, mmio_base + 0x15c0);
826 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x1008;