Lines Matching refs:port_mmio
623 void __iomem *port_mmio = ahci_port_base(ap);
627 tmp = readl(port_mmio + PORT_CMD);
629 writel(tmp, port_mmio + PORT_CMD);
630 readl(port_mmio + PORT_CMD); /* flush */
635 void __iomem *port_mmio = ahci_port_base(ap);
638 tmp = readl(port_mmio + PORT_CMD);
646 writel(tmp, port_mmio + PORT_CMD);
649 tmp = ata_wait_register(port_mmio + PORT_CMD,
659 void __iomem *port_mmio = ahci_port_base(ap);
667 port_mmio + PORT_LST_ADDR_HI);
668 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
672 port_mmio + PORT_FIS_ADDR_HI);
673 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
676 tmp = readl(port_mmio + PORT_CMD);
678 writel(tmp, port_mmio + PORT_CMD);
681 readl(port_mmio + PORT_CMD);
686 void __iomem *port_mmio = ahci_port_base(ap);
690 tmp = readl(port_mmio + PORT_CMD);
692 writel(tmp, port_mmio + PORT_CMD);
695 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
706 void __iomem *port_mmio = ahci_port_base(ap);
709 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
714 writel(cmd, port_mmio + PORT_CMD);
718 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
725 void __iomem *port_mmio = ahci_port_base(ap);
732 scontrol = readl(port_mmio + PORT_SCR_CTL);
734 writel(scontrol, port_mmio + PORT_SCR_CTL);
737 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
739 writel(cmd, port_mmio + PORT_CMD);
826 void __iomem *port_mmio = ahci_port_base(ap);
839 tmp = readl(port_mmio + PORT_SCR_ERR);
841 writel(tmp, port_mmio + PORT_SCR_ERR);
844 tmp = readl(port_mmio + PORT_IRQ_STAT);
847 writel(tmp, port_mmio + PORT_IRQ_STAT);
861 void __iomem *port_mmio = ahci_port_base(ap);
865 tmp = readl(port_mmio + PORT_SIG);
889 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
896 tmp = readl(port_mmio + PORT_CMD);
898 writel(tmp, port_mmio + PORT_CMD);
900 tmp = ata_wait_register(port_mmio + PORT_CMD,
912 void __iomem *port_mmio = ahci_port_base(ap);
962 writel(1, port_mmio + PORT_CMD_ISSUE);
964 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
981 writel(1, port_mmio + PORT_CMD_ISSUE);
982 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1069 void __iomem *port_mmio = ahci_port_base(ap);
1075 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1081 writel(new_tmp, port_mmio + PORT_CMD);
1082 readl(port_mmio + PORT_CMD); /* flush */
1237 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1243 status = readl(port_mmio + PORT_IRQ_STAT);
1244 writel(status, port_mmio + PORT_IRQ_STAT);
1252 qc_active = readl(port_mmio + PORT_SCR_ACT);
1254 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1304 readl(port_mmio + PORT_CMD_ISSUE),
1305 readl(port_mmio + PORT_SCR_ACT),
1388 void __iomem *port_mmio = ahci_port_base(ap);
1391 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1392 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1393 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1400 void __iomem *port_mmio = ahci_port_base(ap);
1403 writel(0, port_mmio + PORT_IRQ_MASK);
1409 void __iomem *port_mmio = ahci_port_base(ap);
1413 tmp = readl(port_mmio + PORT_IRQ_STAT);
1414 writel(tmp, port_mmio + PORT_IRQ_STAT);
1418 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1750 void __iomem *port_mmio = ahci_port_base(ap);
1752 ap->ioaddr.cmd_addr = port_mmio;
1753 ap->ioaddr.scr_addr = port_mmio + PORT_SCR;