Lines Matching defs:pbm
212 static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
216 struct iommu *iommu = pbm->iommu;
245 pbm->name, type_string);
254 unsigned long base = pbm->controller_regs;
285 pbm->name, i, tag, type_string,
290 pbm->name, i, data,
302 struct pci_pbm_info *pbm = dev_id;
303 unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
304 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
323 pbm->name,
331 pbm->name,
335 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
336 printk("%s: UE Secondary errors [", pbm->name);
355 sabre_check_iommu_error(pbm, afsr, afar);
362 struct pci_pbm_info *pbm = dev_id;
363 unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
364 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
382 pbm->name,
390 pbm->name,
395 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
396 printk("%s: CE Secondary errors [", pbm->name);
413 static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm)
419 csr_reg = pbm->controller_regs + SABRE_PCICTRL;
430 pbm->name);
441 pbm->name, stat);
451 struct pci_pbm_info *pbm = dev_id;
456 afsr_reg = pbm->controller_regs + SABRE_PIOAFSR;
457 afar_reg = pbm->controller_regs + SABRE_PIOAFAR;
470 return sabre_pcierr_intr_other(pbm);
475 pbm->name,
485 pbm->name,
488 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
489 printk("%s: PCI Secondary errors [", pbm->name);
521 sabre_check_iommu_error(pbm, afsr, afar);
522 pci_scan_for_target_abort(pbm, pbm->pci_bus);
525 pci_scan_for_master_abort(pbm, pbm->pci_bus);
535 pci_scan_for_parity_error(pbm, pbm->pci_bus);
540 static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
542 struct device_node *dp = pbm->prom_node;
544 unsigned long base = pbm->controller_regs;
548 if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
573 err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
576 pbm->name, err);
582 err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
585 pbm->name, err);
587 "SABRE_PCIERR", pbm);
590 pbm->name, err);
633 static void sabre_scan_bus(struct pci_pbm_info *pbm)
645 pbm->is_66mhz_capable = 1;
647 pbm->is_66mhz_capable = 0;
661 pbm->pci_bus = pci_scan_one_pbm(pbm);
662 if (!pbm->pci_bus)
665 sabre_root_bus = pbm->pci_bus;
667 apb_init(pbm->pci_bus);
669 sabre_register_error_handlers(pbm);
672 static void sabre_iommu_init(struct pci_pbm_info *pbm,
676 struct iommu *iommu = pbm->iommu;
681 iommu->iommu_control = pbm->controller_regs + SABRE_IOMMU_CONTROL;
682 iommu->iommu_tsbbase = pbm->controller_regs + SABRE_IOMMU_TSBBASE;
683 iommu->iommu_flush = pbm->controller_regs + SABRE_IOMMU_FLUSH;
684 iommu->write_complete_reg = pbm->controller_regs + SABRE_WRSYNC;
689 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
691 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
694 sabre_write(pbm->controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
695 sabre_write(pbm->controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
703 sabre_write(pbm->controller_regs + SABRE_IOMMU_TSBBASE,
706 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
721 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
724 static void sabre_pbm_init(struct pci_controller_info *p, struct pci_pbm_info *pbm, struct device_node *dp)
726 pbm->name = dp->full_name;
727 printk("%s: SABRE PCI Bus Module\n", pbm->name);
729 pbm->scan_bus = sabre_scan_bus;
730 pbm->pci_ops = &sun4u_pci_ops;
731 pbm->config_space_reg_bits = 8;
733 pbm->index = pci_num_pbms++;
735 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
736 pbm->parent = p;
737 pbm->prom_node = dp;
738 pci_get_pbm_props(pbm);
740 pci_determine_mem_io_space(pbm);
747 struct pci_pbm_info *pbm;
785 pbm = &p->pbm_A;
786 pbm->iommu = iommu;
790 pbm->next = pci_pbm_root;
791 pci_pbm_root = pbm;
793 pbm->portid = upa_portid;
804 pbm->controller_regs = pr_regs[0].phys_addr;
810 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
814 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
817 sabre_write(pbm->controller_regs + SABRE_PCICTRL,
822 pbm->config_space =
823 (pbm->controller_regs + SABRE_CONFIGSPACE);
847 sabre_iommu_init(pbm, tsbsize, vdma[0], dma_mask);
852 sabre_pbm_init(p, pbm, dp);