Lines Matching refs:dmanr
42 ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr)
44 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
45 printk("set_src_addr: bad channel: %d\n", dmanr);
50 mtdcr(DCRN_DMASAH0 + dmanr*2, (u32)(src_addr >> 32));
52 mtdcr(DCRN_DMASA0 + dmanr*2, (u32)src_addr);
57 ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr)
59 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
60 printk("set_dst_addr: bad channel: %d\n", dmanr);
65 mtdcr(DCRN_DMADAH0 + dmanr*2, (u32)(dst_addr >> 32));
67 mtdcr(DCRN_DMADA0 + dmanr*2, (u32)dst_addr);
72 ppc4xx_enable_dma(unsigned int dmanr)
75 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
82 printk("enable_dma: channel %d in use\n", dmanr);
86 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
87 printk("enable_dma: bad channel: %d\n", dmanr);
93 ppc4xx_set_src_addr(dmanr, 0);
94 ppc4xx_set_dst_addr(dmanr, p_dma_ch->addr);
97 ppc4xx_set_src_addr(dmanr, p_dma_ch->addr);
98 ppc4xx_set_dst_addr(dmanr, 0);
102 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
110 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
119 mtdcr(DCRN_DMASR, status_bits[dmanr]);
137 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
143 ppc4xx_disable_dma(unsigned int dmanr)
146 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
149 printk("disable_dma: channel %d not in use\n", dmanr);
153 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
154 printk("disable_dma: bad channel: %d\n", dmanr);
158 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
160 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
183 ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode)
185 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
187 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
188 printk("set_dma_mode: bad channel 0x%x\n", dmanr);
204 ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count)
206 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
240 mtdcr(DCRN_DMACT0 + (dmanr * 0x8), count);
250 ppc4xx_get_dma_residue(unsigned int dmanr)
253 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
255 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
256 printk("ppc4xx_get_dma_residue: bad channel 0x%x\n", dmanr);
260 count = mfdcr(DCRN_DMACT0 + (dmanr * 0x8));
271 ppc4xx_set_dma_addr(unsigned int dmanr, phys_addr_t addr)
273 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
275 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
276 printk("ppc4xx_set_dma_addr: bad channel: %d\n", dmanr);
319 ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr,
322 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
323 printk("ppc4xx_set_dma_addr2: bad channel: %d\n", dmanr);
329 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
364 ppc4xx_set_src_addr(dmanr, src_dma_addr);
365 ppc4xx_set_dst_addr(dmanr, dst_dma_addr);
377 ppc4xx_enable_dma_interrupt(unsigned int dmanr)
380 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
382 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
383 printk("ppc4xx_enable_dma_interrupt: bad channel: %d\n", dmanr);
389 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
391 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
405 ppc4xx_disable_dma_interrupt(unsigned int dmanr)
408 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
410 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
411 printk("ppc4xx_disable_dma_interrupt: bad channel: %d\n", dmanr);
417 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
419 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
434 ppc4xx_init_dma_channel(unsigned int dmanr, ppc_dma_ch_t * p_init)
438 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
448 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
449 printk("ppc4xx_init_dma_channel: bad channel %d\n", dmanr);
466 polarity &= ~GET_DMA_POLARITY(dmanr);
471 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
503 ppc4xx_get_channel_config(unsigned int dmanr, ppc_dma_ch_t * p_dma_ch)
508 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
509 printk("ppc4xx_get_channel_config: bad channel %d\n", dmanr);
513 memcpy(p_dma_ch, &dma_channels[dmanr], sizeof (ppc_dma_ch_t));
521 p_dma_ch->polarity = polarity & GET_DMA_POLARITY(dmanr);
522 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
544 * Sets the priority for the DMA channel dmanr.
557 ppc4xx_set_channel_priority(unsigned int dmanr, unsigned int priority)
561 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
562 printk("ppc4xx_set_channel_priority: bad channel %d\n", dmanr);
572 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
574 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
593 ppc4xx_get_peripheral_width(unsigned int dmanr)
597 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
598 printk("ppc4xx_get_peripheral_width: bad channel %d\n", dmanr);
602 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
611 ppc4xx_clr_dma_status(unsigned int dmanr)
613 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
614 printk(KERN_ERR "ppc4xx_clr_dma_status: bad channel: %d\n", dmanr);
617 mtdcr(DCRN_DMASR, ((u32)DMA_CH0_ERR | (u32)DMA_CS0 | (u32)DMA_TS0) >> dmanr);
630 ppc4xx_enable_burst(unsigned int dmanr)
633 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
634 printk(KERN_ERR "ppc4xx_enable_burst: bad channel: %d\n", dmanr);
637 ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) | DMA_CTC_BTEN;
638 mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
649 ppc4xx_disable_burst(unsigned int dmanr)
652 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
653 printk(KERN_ERR "ppc4xx_disable_burst: bad channel: %d\n", dmanr);
656 ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BTEN;
657 mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
674 ppc4xx_set_burst_size(unsigned int dmanr, unsigned int bsize)
677 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
678 printk(KERN_ERR "ppc4xx_set_burst_size: bad channel: %d\n", dmanr);
681 ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BSIZ_MSK;
683 mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);