Lines Matching refs:control
74 unsigned int control;
102 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
104 control &= ~(DMA_TM_MASK | DMA_TD); /* clear all mode bits */
107 control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
110 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
129 control |= DMA_TCE_ENABLE;
135 control |= (p_dma_ch->mode | DMA_CE_ENABLE);
137 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
145 unsigned int control;
158 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
159 control &= ~DMA_CE_ENABLE;
160 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
379 unsigned int control;
389 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
390 control |= DMA_CIE_ENABLE; /* Channel Interrupt Enable */
391 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
407 unsigned int control;
417 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
418 control &= ~DMA_CIE_ENABLE; /* Channel Interrupt Enable */
419 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
437 uint32_t control = 0;
459 /* Setup the control register based on the values passed to
460 * us in p_init. Then, over-write the control register with this
463 control |= SET_DMA_CONTROL;
471 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
477 * The peripheral width values written in the control register are:
491 * Save the control word for easy access.
493 p_dma_ch->control = control;
506 unsigned int control;
522 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
524 p_dma_ch->cp = GET_DMA_PRIORITY(control);
525 p_dma_ch->pwidth = GET_DMA_PW(control);
526 p_dma_ch->psc = GET_DMA_PSC(control);
527 p_dma_ch->pwc = GET_DMA_PWC(control);
528 p_dma_ch->phc = GET_DMA_PHC(control);
529 p_dma_ch->ce = GET_DMA_CE_ENABLE(control);
530 p_dma_ch->int_enable = GET_DMA_CIE_ENABLE(control);
531 p_dma_ch->shift = GET_DMA_PW(control);
534 p_dma_ch->pf = GET_DMA_PREFETCH(control);
536 p_dma_ch->ch_enable = GET_DMA_CH(control);
537 p_dma_ch->ece_enable = GET_DMA_ECE(control);
538 p_dma_ch->tcd_disable = GET_DMA_TCD(control);
559 unsigned int control;
572 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
573 control |= SET_DMA_PRIORITY(priority);
574 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
595 unsigned int control;
602 control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
604 return (GET_DMA_PW(control));
623 * Enables the burst on the channel (BTEN bit in the control/count register)
642 * Disables the burst on the channel (BTEN bit in the control/count register)
662 * (BSIZ bits in the control/count register))