Lines Matching refs:si
167 struct mv64x60_setup_info si;
173 memset(&si, 0, sizeof(si));
175 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
178 si.pci_0.enable_bus = 1;
179 si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
180 si.pci_0.pci_io.pci_base_hi = 0;
181 si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
182 si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
183 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
184 si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
185 si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
186 si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
187 si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
188 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
189 si.pci_0.pci_cmd_bits = 0;
190 si.pci_0.latency_timer = 0x80;
194 si.cpu_prot_options[i] = 0;
195 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
196 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
197 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
199 si.pci_1.acc_cntl_options[i] =
205 si.cpu_prot_options[i] = 0;
206 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
207 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
208 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
210 si.pci_1.acc_cntl_options[i] =
219 if (mv64x60_init(&bh, &si)) {