Lines Matching refs:RB
409 /* The RB field in an X, XO, M, or MDS form instruction. */
410 #define RB RAOPT + 1
414 /* The RB field in an X form instruction when it must be the same as
417 #define RBS RB + 1
1354 /* The RB field in an X form instruction when it must be the same as
1684 /* An X_MASK with the RB field fixed. */
1693 /* An X_MASK with the RA and RB fields fixed. */
1788 /* An XO_MASK with the RB field fixed. */
1987 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1988 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1989 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1990 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1991 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1992 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1993 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1994 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1995 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1996 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1997 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1998 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1999 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2000 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2001 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2002 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2003 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2004 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2005 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2006 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2007 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2008 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2009 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2010 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2011 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2012 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2013 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2014 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2015 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2016 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2017 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2018 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2019 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2020 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2021 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2022 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2023 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2024 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2025 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2026 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2027 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2028 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2029 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2030 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2031 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2032 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2033 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2034 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2035 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2036 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2037 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2038 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2039 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2040 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2041 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2042 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2043 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2044 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2045 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2046 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2047 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2048 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2049 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2050 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2051 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2052 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2053 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2054 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2055 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2056 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2057 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2058 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2059 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2060 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2061 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2062 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2063 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2067 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2068 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2069 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2070 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2077 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2081 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2082 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2083 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2084 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2085 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2086 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2087 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2088 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2089 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2090 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2091 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2092 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2093 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2094 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2095 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2096 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2097 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2098 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2099 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2100 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2101 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2102 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2103 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2104 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2105 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2264 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2265 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2266 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2267 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2268 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2269 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2278 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2281 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2283 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2285 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2286 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2287 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2289 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2295 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2296 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2301 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2302 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2303 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2304 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2307 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2308 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2309 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2310 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2311 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2314 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2316 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2318 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2320 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2322 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2324 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2326 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2328 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2330 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2332 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2334 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2337 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2339 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2343 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2345 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2347 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2349 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2354 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2355 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2357 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2358 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2359 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2360 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2361 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2362 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2363 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2364 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2365 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2366 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2367 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2368 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2369 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2370 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2371 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2372 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2373 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2378 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2379 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2380 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2381 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2382 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2383 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2384 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2385 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2386 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2387 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2388 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2389 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2390 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2391 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2392 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2393 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2394 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2395 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2396 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2397 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2399 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2400 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2401 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2402 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2403 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2404 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2405 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2406 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2407 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2408 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2409 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2410 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2411 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2412 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2413 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2414 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2416 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2417 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2418 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2419 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2420 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2421 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2422 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2423 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2424 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2425 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2426 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2427 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2429 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2430 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2431 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2432 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2433 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2434 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2435 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2436 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2437 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2438 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2439 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2440 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2442 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2443 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2444 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2445 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2446 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2447 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2449 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2450 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2451 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2452 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2453 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2454 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2456 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2457 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2458 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2459 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2460 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2461 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2462 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2463 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2465 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2466 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2468 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2469 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2470 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2471 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2473 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2474 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2475 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2476 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2478 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2479 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2480 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2481 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2482 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2483 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2484 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2485 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2487 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2488 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2489 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2490 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2492 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2493 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2494 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2495 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2509 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2510 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
3265 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3266 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3273 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3274 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3275 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3276 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3277 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3278 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3315 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3316 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3317 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3318 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3320 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3321 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3323 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3324 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3325 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3326 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3328 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3329 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3330 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3331 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3332 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3333 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3334 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3335 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3336 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3337 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3338 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3339 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3340 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3341 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3342 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3343 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3344 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3345 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3346 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3347 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3348 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3349 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3350 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3351 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3352 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3353 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3354 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3355 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3357 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3358 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3360 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3361 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3362 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3363 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3364 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3365 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3366 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3367 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3368 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3369 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3370 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3371 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3373 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3374 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3376 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3377 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3378 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3379 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3380 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3381 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3382 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3383 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3385 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3386 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3388 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3389 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3390 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3391 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3397 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3399 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3401 { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3402 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3404 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3405 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3407 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3408 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3409 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3410 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3417 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3418 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3420 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3421 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3423 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3424 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3426 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3428 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3430 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3431 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3432 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3433 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3435 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3436 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3437 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3438 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3439 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3440 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3441 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3442 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3444 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3446 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3448 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3449 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3451 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3453 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3458 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3459 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3461 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3462 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3463 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3464 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3465 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3466 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3467 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3468 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3469 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3470 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3471 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3472 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3473 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3474 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3475 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3477 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3478 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3480 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3481 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3483 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3484 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3490 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3492 { "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3493 { "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
3495 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3497 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3499 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3506 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3507 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3508 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3509 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3511 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3513 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3515 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3520 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3522 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3524 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3526 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3530 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3532 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3533 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3534 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3535 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3536 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3537 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3538 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3539 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3541 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3542 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3543 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3544 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3545 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3546 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3547 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3548 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3550 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3558 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3560 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3562 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3563 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3565 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3567 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3569 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3570 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3572 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3573 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3579 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3580 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3584 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3586 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3587 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3594 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3616 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3618 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3620 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3621 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3623 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3624 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3626 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3628 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3639 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3640 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3641 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3642 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3653 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3654 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3655 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3656 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3657 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3658 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3659 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3660 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3662 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3663 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3664 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3666 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3668 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3673 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3675 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3679 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3680 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3681 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3682 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3684 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3685 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3686 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3687 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3688 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3689 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3690 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3691 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3693 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3697 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3698 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3700 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3702 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3704 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3705 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3707 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3709 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3711 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3712 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3714 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3716 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3718 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3719 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3721 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3759 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3760 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3761 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3762 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3955 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3957 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3958 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3960 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3962 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3964 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3965 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3967 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3974 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3975 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3976 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3977 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3981 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3983 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3985 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3989 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3991 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3992 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3994 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3995 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3997 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3999 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
4001 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
4003 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4005 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4007 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4009 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4011 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4013 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4015 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4017 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4018 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4023 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4025 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
4027 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4029 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4031 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4034 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4036 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4077 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4078 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4079 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4080 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4085 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4086 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4087 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4088 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4244 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4246 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4247 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4249 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4251 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4255 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4264 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4265 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4266 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4267 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4272 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4273 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4274 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4275 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4277 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4283 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4292 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4294 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4295 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4297 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4298 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4300 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4302 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4303 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4304 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4305 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4307 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4308 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4310 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4311 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4313 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4314 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4316 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4318 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4324 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4326 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4339 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4341 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4343 { "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4345 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4349 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4351 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4353 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4355 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4357 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4358 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4360 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4361 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4363 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4365 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4366 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4368 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4369 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4371 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4373 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4375 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4380 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4385 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4387 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4388 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4390 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4391 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4393 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4397 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4399 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4404 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4406 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4408 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4409 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4411 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4413 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4415 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4416 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4417 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4418 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4420 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4421 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4423 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4425 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4426 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4428 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4430 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4440 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4442 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4447 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4449 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4451 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4452 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4453 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4454 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4456 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4458 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4460 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4462 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4463 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4465 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4466 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4473 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4475 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4481 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4489 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4491 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4496 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4498 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4500 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4502 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4507 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4509 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4510 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4512 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4514 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4516 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4517 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4518 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4520 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4522 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4523 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4524 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4525 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4526 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4527 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4528 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4529 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4530 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4531 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4532 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4533 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4536 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4537 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4538 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4539 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4540 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4541 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4542 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4543 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },