Lines Matching refs:csa
85 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
101 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
113 if (csa) {
114 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
115 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
116 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
125 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
138 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
149 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
159 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
174 if (csa) {
175 csa->priv2.mfc_control_RW =
185 if (csa) {
186 csa->priv2.mfc_control_RW =
194 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
202 csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
205 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
210 csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
213 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
221 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
233 csa->prob.spu_status_R = SPU_STATUS_RUNNING;
235 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
239 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
248 csa->priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
249 csa->suspend_time = get_cycles();
252 csa->spu_chnldata_RW[7] = in_be64(&priv2->spu_chnldata_RW);
255 csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
259 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
271 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
277 csa->suspend_time = get_cycles();
280 static inline void remove_other_spu_access(struct spu_state *csa,
289 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
302 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
314 static inline void handle_pending_interrupts(struct spu_state *csa,
328 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
339 csa->priv2.puq[i].mfc_cq_data0_RW =
341 csa->priv2.puq[i].mfc_cq_data1_RW =
343 csa->priv2.puq[i].mfc_cq_data2_RW =
345 csa->priv2.puq[i].mfc_cq_data3_RW =
349 csa->priv2.spuq[i].mfc_cq_data0_RW =
351 csa->priv2.spuq[i].mfc_cq_data1_RW =
353 csa->priv2.spuq[i].mfc_cq_data2_RW =
355 csa->priv2.spuq[i].mfc_cq_data3_RW =
361 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
369 csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
372 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
380 csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
383 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
391 csa->priv2.spu_tag_status_query_RW =
395 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
403 csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
404 csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
407 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
415 csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
418 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
424 csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
427 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
438 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
450 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
463 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
481 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
488 csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
491 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
498 csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
501 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
513 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
520 csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
523 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
535 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
542 csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
545 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
553 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
559 csa->priv1.resource_allocation_groupID_RW =
561 csa->priv1.resource_allocation_enable_RW =
565 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
572 csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
575 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
582 csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
585 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
592 csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
595 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
606 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
613 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
614 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
621 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
631 csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
633 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
639 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
648 csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
652 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
672 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
707 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu)
728 get_kernel_slb((unsigned long)csa->lscsa, lscsa_slb);
734 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
746 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
803 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
805 unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
819 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
836 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
849 addr64.ull = (u64) csa->lscsa;
854 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
867 addr64.ull = (u64) csa->lscsa;
872 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
888 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
901 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
924 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
943 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
958 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
966 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
980 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
994 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
1036 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1070 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1095 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1115 static inline void setup_spu_status_part1(struct spu_state *csa,
1141 (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1142 if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1148 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1149 csa->lscsa->stopped_status.slot[1] = status_code;
1151 } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1157 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1158 csa->lscsa->stopped_status.slot[1] = status_code;
1160 } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1165 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1166 csa->lscsa->stopped_status.slot[1] = status_code;
1168 } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1173 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1174 csa->lscsa->stopped_status.slot[1] = status_code;
1176 } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1181 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1182 csa->lscsa->stopped_status.slot[1] = status_code;
1184 } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1189 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1191 } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1195 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1197 } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1202 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1207 static inline void setup_spu_status_part2(struct spu_state *csa,
1226 if (!(csa->prob.spu_status_R & mask)) {
1227 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1231 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1238 csa->priv1.resource_allocation_groupID_RW);
1240 csa->priv1.resource_allocation_enable_RW);
1243 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1259 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1268 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1270 cycles_t delta_time = resume_time - csa->suspend_time;
1272 csa->lscsa->decr.slot[0] -= delta_time;
1276 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1281 csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1284 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1289 csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1292 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1307 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1314 out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1318 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1330 if (csa->prob.spu_status_R & mask) {
1338 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1353 if (!(csa->prob.spu_status_R & mask)) {
1365 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1367 unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1381 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1401 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1410 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1413 csa->priv2.puq[i].mfc_cq_data0_RW);
1415 csa->priv2.puq[i].mfc_cq_data1_RW);
1417 csa->priv2.puq[i].mfc_cq_data2_RW);
1419 csa->priv2.puq[i].mfc_cq_data3_RW);
1423 csa->priv2.spuq[i].mfc_cq_data0_RW);
1425 csa->priv2.spuq[i].mfc_cq_data1_RW);
1427 csa->priv2.spuq[i].mfc_cq_data2_RW);
1429 csa->priv2.spuq[i].mfc_cq_data3_RW);
1435 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1442 out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1446 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1453 out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1457 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1465 csa->priv2.spu_tag_status_query_RW);
1469 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1477 out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1478 out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1482 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1489 out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1492 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1497 spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1501 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1514 ch0_cnt = csa->spu_chnlcnt_RW[0];
1515 ch0_data = csa->spu_chnldata_RW[0];
1516 ch1_data = csa->spu_chnldata_RW[1];
1517 csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1520 csa->spu_chnlcnt_RW[0] = 1;
1524 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1531 if (csa->lscsa->decr_status.slot[0] == 1) {
1532 csa->spu_chnldata_RW[0] |= 0x20;
1534 if ((csa->lscsa->decr_status.slot[0] == 1) &&
1535 (csa->spu_chnlcnt_RW[0] == 0 &&
1536 ((csa->spu_chnldata_RW[2] & 0x20) == 0x0) &&
1537 ((csa->spu_chnldata_RW[0] & 0x20) != 0x1))) {
1538 csa->spu_chnlcnt_RW[0] = 1;
1542 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1553 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[1]);
1560 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1561 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1566 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1578 ch_counts[1] = csa->spu_chnlcnt_RW[21];
1589 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1596 out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1600 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1607 out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1611 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1619 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1626 out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1630 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1640 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1642 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1647 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1656 if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1662 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1671 if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1679 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1684 spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1688 static inline void restore_other_spu_access(struct spu_state *csa,
1696 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1704 if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1710 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1717 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1719 if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1725 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1735 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1744 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1750 spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1751 spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1752 spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
2130 static void init_prob(struct spu_state *csa)
2132 csa->spu_chnlcnt_RW[9] = 1;
2133 csa->spu_chnlcnt_RW[21] = 16;
2134 csa->spu_chnlcnt_RW[23] = 1;
2135 csa->spu_chnlcnt_RW[28] = 1;
2136 csa->spu_chnlcnt_RW[30] = 1;
2137 csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2138 csa->prob.mb_stat_R = 0x000400;
2141 static void init_priv1(struct spu_state *csa)
2144 csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2150 csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2153 csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2155 csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2160 static void init_priv2(struct spu_state *csa)
2162 csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2163 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2179 int spu_init_csa(struct spu_state *csa)
2183 if (!csa)
2185 memset(csa, 0, sizeof(struct spu_state));
2187 rc = spu_alloc_lscsa(csa);
2191 spin_lock_init(&csa->register_lock);
2193 init_prob(csa);
2194 init_priv1(csa);
2195 init_priv2(csa);
2201 void spu_fini_csa(struct spu_state *csa)
2203 spu_free_lscsa(csa);