Lines Matching refs:csa
54 ch0_cnt = ctx->csa.spu_chnlcnt_RW[0];
55 ch0_data = ctx->csa.spu_chnldata_RW[0];
56 ch1_data = ctx->csa.spu_chnldata_RW[1];
57 ctx->csa.spu_chnldata_RW[0] |= event;
59 ctx->csa.spu_chnlcnt_RW[0] = 1;
68 spin_lock(&ctx->csa.register_lock);
69 mbox_stat = ctx->csa.prob.mb_stat_R;
75 *data = ctx->csa.prob.pu_mb_R;
76 ctx->csa.prob.mb_stat_R &= ~(0x0000ff);
77 ctx->csa.spu_chnlcnt_RW[28] = 1;
81 spin_unlock(&ctx->csa.register_lock);
87 return ctx->csa.prob.mb_stat_R;
97 spin_lock_irq(&ctx->csa.register_lock);
98 stat = ctx->csa.prob.mb_stat_R;
109 ctx->csa.priv1.int_stat_class0_RW &= ~0x1;
110 ctx->csa.priv1.int_mask_class2_RW |= 0x1;
117 ctx->csa.priv1.int_stat_class0_RW &= ~0x10;
118 ctx->csa.priv1.int_mask_class2_RW |= 0x10;
121 spin_unlock_irq(&ctx->csa.register_lock);
129 spin_lock(&ctx->csa.register_lock);
130 if (ctx->csa.prob.mb_stat_R & 0xff0000) {
135 *data = ctx->csa.priv2.puint_mb_R;
136 ctx->csa.prob.mb_stat_R &= ~(0xff0000);
137 ctx->csa.spu_chnlcnt_RW[30] = 1;
142 ctx->csa.priv1.int_mask_class2_RW |= 0x1UL;
145 spin_unlock(&ctx->csa.register_lock);
153 spin_lock(&ctx->csa.register_lock);
154 if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) {
155 int slot = ctx->csa.spu_chnlcnt_RW[29];
156 int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8;
163 ctx->csa.spu_mailbox_data[slot] = data;
164 ctx->csa.spu_chnlcnt_RW[29] = ++slot;
165 ctx->csa.prob.mb_stat_R = (((4 - slot) & 0xff) << 8);
171 ctx->csa.priv1.int_mask_class2_RW |= 0x10;
174 spin_unlock(&ctx->csa.register_lock);
180 return ctx->csa.spu_chnldata_RW[3];
185 spin_lock(&ctx->csa.register_lock);
186 if (ctx->csa.priv2.spu_cfg_RW & 0x1)
187 ctx->csa.spu_chnldata_RW[3] |= data;
189 ctx->csa.spu_chnldata_RW[3] = data;
190 ctx->csa.spu_chnlcnt_RW[3] = 1;
192 spin_unlock(&ctx->csa.register_lock);
197 return ctx->csa.spu_chnldata_RW[4];
202 spin_lock(&ctx->csa.register_lock);
203 if (ctx->csa.priv2.spu_cfg_RW & 0x2)
204 ctx->csa.spu_chnldata_RW[4] |= data;
206 ctx->csa.spu_chnldata_RW[4] = data;
207 ctx->csa.spu_chnlcnt_RW[4] = 1;
209 spin_unlock(&ctx->csa.register_lock);
216 spin_lock(&ctx->csa.register_lock);
217 tmp = ctx->csa.priv2.spu_cfg_RW;
222 ctx->csa.priv2.spu_cfg_RW = tmp;
223 spin_unlock(&ctx->csa.register_lock);
228 return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0);
235 spin_lock(&ctx->csa.register_lock);
236 tmp = ctx->csa.priv2.spu_cfg_RW;
241 ctx->csa.priv2.spu_cfg_RW = tmp;
242 spin_unlock(&ctx->csa.register_lock);
247 return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0);
252 return ctx->csa.prob.spu_npc_RW;
257 ctx->csa.prob.spu_npc_RW = val;
262 return ctx->csa.prob.spu_status_R;
267 return ctx->csa.lscsa->ls;
272 return ctx->csa.prob.spu_runcntl_RW;
277 spin_lock(&ctx->csa.register_lock);
278 ctx->csa.prob.spu_runcntl_RW = val;
280 ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING;
282 ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING;
284 spin_unlock(&ctx->csa.register_lock);
289 struct spu_state *csa = &ctx->csa;
292 spin_lock(&csa->register_lock);
293 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
294 csa->priv1.mfc_sr1_RW = sr1;
295 spin_unlock(&csa->register_lock);
300 struct spu_state *csa = &ctx->csa;
303 spin_lock(&csa->register_lock);
304 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
305 csa->priv1.mfc_sr1_RW = sr1;
306 spin_unlock(&csa->register_lock);
312 struct spu_problem_collapsed *prob = &ctx->csa.prob;
315 spin_lock(&ctx->csa.register_lock);
323 spin_unlock(&ctx->csa.register_lock);
330 return ctx->csa.prob.dma_tagstatus_R;
335 return ctx->csa.prob.dma_qstatus_R;
343 spin_lock(&ctx->csa.register_lock);
345 spin_unlock(&ctx->csa.register_lock);