Lines Matching refs:r3
91 * r3: 'BooX' (0x426f6f58)
96 * r3: 'APUS'
104 * r3: ptr to residual data
136 cmpw 0,r3,r31
142 1: mr r31,r3 /* save parameters */
161 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
195 mr r26,r3
196 addis r4,r3,KERNELBASE@h /* current address of _start */
223 li r3,1 /* MTX only has 1 cpu */
227 stw r3,__secondary_hold_acknowledge@l(0)
231 cmpw 0,r4,r3
234 mr r24,r3 /* cpu # */
312 addi r3,r1,STACK_FRAME_OVERHEAD; \
375 addi r3,r1,STACK_FRAME_OVERHEAD
394 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
408 li r3,0 /* into the hash table */
426 addi r3,r1,STACK_FRAME_OVERHEAD
444 addi r3,r1,STACK_FRAME_OVERHEAD
479 * Note: we get an alternate set of r0 - r3 to use automatically.
487 * r3: scratch
491 mfspr r3,SPRN_IMISS
493 cmplw 0,r3,r1
503 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
507 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
508 lwz r3,0(r2) /* get linux-style pte */
509 andc. r1,r1,r3 /* check access & ~permission */
511 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
516 stw r3,0(r2) /* update PTE (accessed bit) */
518 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
519 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
521 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
522 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
524 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
526 mfspr r3,SPRN_IMISS
527 tlbli r3
528 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
529 mtcrf 0x80,r3
532 mfspr r3,SPRN_SRR1
533 rlwinm r1,r3,9,6,6 /* Get load/store bit */
538 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
548 mtcrf 0x80,r3 /* Restore CR0 */
561 * r3: scratch
565 mfspr r3,SPRN_DMISS
567 cmplw 0,r3,r1
577 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
581 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
582 lwz r3,0(r2) /* get linux-style pte */
583 andc. r1,r1,r3 /* check access & ~permission */
585 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
590 stw r3,0(r2) /* update PTE (accessed bit) */
592 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
593 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
595 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
596 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
598 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
600 mfspr r3,SPRN_DMISS
601 tlbld r3
602 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
603 mtcrf 0x80,r3
606 mfspr r3,SPRN_SRR1
607 rlwinm r1,r3,9,6,6 /* Get load/store bit */
611 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
620 mtcrf 0x80,r3 /* Restore CR0 */
633 * r3: scratch
637 mfspr r3,SPRN_DMISS
639 cmplw 0,r3,r1
649 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
653 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
654 lwz r3,0(r2) /* get linux-style pte */
655 andc. r1,r1,r3 /* check access & ~permission */
657 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
662 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
664 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
666 andc r1,r3,r1 /* PP = user? 2: 0 */
668 mfspr r3,SPRN_DMISS
669 tlbld r3
670 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
671 mtcrf 0x80,r3
718 addi r3,r1,STACK_FRAME_OVERHEAD
723 addi r3,r1,STACK_FRAME_OVERHEAD
749 addis r3,r6,last_task_used_altivec@ha
750 lwz r4,last_task_used_altivec@l(r3)
779 stw r4,last_task_used_altivec@l(r3)
790 lwz r3,_MSR(r1)
791 oris r3,r3,MSR_VEC@h
792 stw r3,_MSR(r1) /* enable use of AltiVec after return */
793 lis r3,87f@h
794 ori r3,r3,87f@l
816 cmpwi 0,r3,0
818 addi r3,r3,THREAD /* want THREAD of task */
819 lwz r5,PT_REGS(r3)
821 SAVE_32VRS(0, r4, r3)
824 stvx vr0,r4,r3
827 lis r3,MSR_VEC@h
828 andc r4,r4,r3 /* disable AltiVec for previous task */
847 li r3,0 /* Destination base address */
851 addi r0,r3,4f@l /* jump to the address of 4f */
861 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
862 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
871 stwx r0,r6,r3
873 dcbst r6,r3 /* write it to memory */
875 icbi r6,r3 /* flush the icache line */
969 li r3,0
970 ori r3,r3,HID0_ICE
971 andc r4,r4,r3
979 mfspr r3, SPRN_PIR
980 stw r3, __secondary_hold_acknowledge@l(0)
981 mr r24, r3 /* cpu # */
1008 lis r3,-KERNELBASE@h
1012 lis r3,-KERNELBASE@h
1026 tophys(r3,r1)
1027 stw r0,0(r3)
1037 li r3,0
1038 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1043 lis r3,start_secondary@h
1044 ori r3,r3,start_secondary@l
1045 mtspr SPRN_SRR0,r3
1080 lis r3,0x2000 /* Ku = 1, VSID = 0 */
1082 3: mtsrin r3,r4
1083 addi r3,r3,0x111 /* increment VSID */
1089 mfpvr r3
1090 srwi r3,r3,16
1091 cmpwi r3,1
1092 lis r3,BATS@ha
1093 addi r3,r3,BATS@l
1094 tophys(r3,r3)
1095 LOAD_BAT(0,r3,r4,r5)
1096 LOAD_BAT(1,r3,r4,r5)
1097 LOAD_BAT(2,r3,r4,r5)
1098 LOAD_BAT(3,r3,r4,r5)
1100 LOAD_BAT(4,r3,r4,r5)
1101 LOAD_BAT(5,r3,r4,r5)
1102 LOAD_BAT(6,r3,r4,r5)
1103 LOAD_BAT(7,r3,r4,r5)
1120 li r3,0
1121 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1132 mr r3,r31
1142 lis r3,0xfff0 /* Copy to 0xfff00000 */
1144 lis r3,0 /* Copy to 0x00000000 */
1159 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1160 FIX_SRR1(r3,r5)
1162 mtspr SPRN_SRR1,r3
1185 lis r3,start_kernel@h
1186 ori r3,r3,start_kernel@l
1187 mtspr SPRN_SRR0,r3
1196 mulli r3,r3,897 /* multiply context by skew factor */
1197 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1198 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1213 mtsrin r3,r4
1214 addi r3,r3,0x111 /* next VSID */
1215 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1289 addi r4, r3, __after_mmu_off - _start
1290 mfmsr r3
1291 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1293 andc r3,r3,r0
1295 mtspr SPRN_SRR1,r3
1349 addis r8,r3,disp_BAT@ha
1371 * r3 is the board info structure, r4 is the location for starting.