Lines Matching defs:irq_nr
73 static void end_irq(unsigned int irq_nr);
74 static inline void mask_and_ack_level_irq(unsigned int irq_nr);
75 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
76 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
77 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr);
78 inline void local_enable_irq(unsigned int irq_nr);
79 inline void local_disable_irq(unsigned int irq_nr);
86 inline void local_enable_irq(unsigned int irq_nr)
88 if (irq_nr > AU1000_LAST_INTC0_INT) {
89 au_writel(1<<(irq_nr-32), IC1_MASKSET);
90 au_writel(1<<(irq_nr-32), IC1_WAKESET);
93 au_writel(1<<irq_nr, IC0_MASKSET);
94 au_writel(1<<irq_nr, IC0_WAKESET);
100 inline void local_disable_irq(unsigned int irq_nr)
102 if (irq_nr > AU1000_LAST_INTC0_INT) {
103 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
104 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
107 au_writel(1<<irq_nr, IC0_MASKCLR);
108 au_writel(1<<irq_nr, IC0_WAKECLR);
114 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
116 if (irq_nr > AU1000_LAST_INTC0_INT) {
117 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
118 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
121 au_writel(1<<irq_nr, IC0_RISINGCLR);
122 au_writel(1<<irq_nr, IC0_MASKCLR);
128 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
130 if (irq_nr > AU1000_LAST_INTC0_INT) {
131 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
132 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
135 au_writel(1<<irq_nr, IC0_FALLINGCLR);
136 au_writel(1<<irq_nr, IC0_MASKCLR);
142 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
147 if (irq_nr > AU1000_LAST_INTC0_INT) {
148 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
149 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
150 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
153 au_writel(1<<irq_nr, IC0_FALLINGCLR);
154 au_writel(1<<irq_nr, IC0_RISINGCLR);
155 au_writel(1<<irq_nr, IC0_MASKCLR);
161 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
164 local_disable_irq(irq_nr);
167 if (irq_nr == AU1000_GPIO_15) {
176 static void end_irq(unsigned int irq_nr)
178 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
179 local_enable_irq(irq_nr);
182 if (irq_nr == AU1000_GPIO_15) {
302 static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
304 if (irq_nr > AU1000_MAX_INTR) return;
306 if (irq_nr > AU1000_LAST_INTC0_INT) {
309 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
310 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
311 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
312 set_irq_chip(irq_nr, &rise_edge_irq_type);
315 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
316 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
317 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
318 set_irq_chip(irq_nr, &fall_edge_irq_type);
321 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
322 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
323 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
324 set_irq_chip(irq_nr, &either_edge_irq_type);
327 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
328 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
329 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
330 set_irq_chip(irq_nr, &level_irq_type);
333 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
334 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
335 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
336 set_irq_chip(irq_nr, &level_irq_type);
339 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
340 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
341 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
344 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
345 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
346 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
347 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
351 au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
353 au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
354 au_writel(1<<(irq_nr-32), IC1_SRCSET);
355 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
356 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
361 au_writel(1<<irq_nr, IC0_CFG2CLR);
362 au_writel(1<<irq_nr, IC0_CFG1CLR);
363 au_writel(1<<irq_nr, IC0_CFG0SET);
364 set_irq_chip(irq_nr, &rise_edge_irq_type);
367 au_writel(1<<irq_nr, IC0_CFG2CLR);
368 au_writel(1<<irq_nr, IC0_CFG1SET);
369 au_writel(1<<irq_nr, IC0_CFG0CLR);
370 set_irq_chip(irq_nr, &fall_edge_irq_type);
373 au_writel(1<<irq_nr, IC0_CFG2CLR);
374 au_writel(1<<irq_nr, IC0_CFG1SET);
375 au_writel(1<<irq_nr, IC0_CFG0SET);
376 set_irq_chip(irq_nr, &either_edge_irq_type);
379 au_writel(1<<irq_nr, IC0_CFG2SET);
380 au_writel(1<<irq_nr, IC0_CFG1CLR);
381 au_writel(1<<irq_nr, IC0_CFG0SET);
382 set_irq_chip(irq_nr, &level_irq_type);
385 au_writel(1<<irq_nr, IC0_CFG2SET);
386 au_writel(1<<irq_nr, IC0_CFG1SET);
387 au_writel(1<<irq_nr, IC0_CFG0CLR);
388 set_irq_chip(irq_nr, &level_irq_type);
391 au_writel(1<<irq_nr, IC0_CFG0CLR);
392 au_writel(1<<irq_nr, IC0_CFG1CLR);
393 au_writel(1<<irq_nr, IC0_CFG2CLR);
396 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
397 au_writel(1<<irq_nr, IC0_CFG0CLR);
398 au_writel(1<<irq_nr, IC0_CFG1CLR);
399 au_writel(1<<irq_nr, IC0_CFG2CLR);
403 au_writel(1<<irq_nr, IC0_ASSIGNCLR);
405 au_writel(1<<irq_nr, IC0_ASSIGNSET);
406 au_writel(1<<irq_nr, IC0_SRCSET);
407 au_writel(1<<irq_nr, IC0_MASKCLR);
408 au_writel(1<<irq_nr, IC0_WAKECLR);