Lines Matching refs:temp1
394 #define temp1 r2 /* careful, it overlaps with input registers */
446 add temp1=temp2, regs // struct ia64_sal_os_state on MCA or INIT stack
449 mov regs=temp1 // save the start of sos
450 st8 [temp1]=r1,16 // os_gp
453 st8 [temp1]=r9,16 // sal_proc
457 st8 [temp1]=r18 // proc_state_param
460 add temp1=SOS(SAL_RA), regs
463 st8 [temp1]=r12,16 // sal_ra
467 st8 [temp1]=r17,16 // pal_min_state
471 st8 [temp1]=r6,16 // prev_IA64_KR_CURRENT_STACK
475 st8 [temp1]=r12,16 // cr.isr
479 st8 [temp1]=r12,16 // cr.itir
483 st8 [temp1]=r12 // cr.iim
487 add temp1=SOS(OS_STATUS), regs
491 st8 [temp1]=r12 // os_status, default is cold boot
500 add temp1=PT(B6), regs
505 st8 [temp1]=temp3,PT(AR_CSD)-PT(B6) // save b6
511 st8 [temp1]=temp3,PT(AR_UNAT)-PT(AR_CSD) // save ar.csd
516 st8 [temp1]=temp3,PT(AR_RNAT)-PT(AR_UNAT) // save ar.unat
521 st8 [temp1]=temp3,PT(LOADRS)-PT(AR_RNAT) // save ar.rnat
530 st8 [temp1]=temp3,PT(AR_CCV)-PT(LOADRS) // save loadrs
534 st8 [temp1]=temp3,PT(F7)-PT(AR_CCV) // save ar.ccv
537 stf.spill [temp1]=f7,PT(F9)-PT(F7)
540 stf.spill [temp1]=f9,PT(F11)-PT(F9)
543 stf.spill [temp1]=f11
549 add temp1=SW(F2), regs
552 stf.spill [temp1]=f2,32
555 stf.spill [temp1]=f4,32
558 stf.spill [temp1]=f12,32
561 stf.spill [temp1]=f14,32
564 stf.spill [temp1]=f16,32
567 stf.spill [temp1]=f18,32
570 stf.spill [temp1]=f20,32
573 stf.spill [temp1]=f22,32
576 stf.spill [temp1]=f24,32
579 stf.spill [temp1]=f26,32
582 stf.spill [temp1]=f28,32
585 stf.spill [temp1]=f30,SW(B2)-SW(F30)
590 st8 [temp1]=temp3,16 // save b2
595 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
599 st8 [temp1]=temp3 // save ar.lc
707 add temp1=SW(F2), regs
710 ldf.fill f2=[temp1],32
713 ldf.fill f4=[temp1],32
716 ldf.fill f12=[temp1],32
719 ldf.fill f14=[temp1],32
722 ldf.fill f16=[temp1],32
725 ldf.fill f18=[temp1],32
728 ldf.fill f20=[temp1],32
731 ldf.fill f22=[temp1],32
734 ldf.fill f24=[temp1],32
737 ldf.fill f26=[temp1],32
740 ldf.fill f28=[temp1],32
743 ldf.fill f30=[temp1],SW(B2)-SW(F30)
746 ld8 temp3=[temp1],16 // restore b2
751 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
756 ld8 temp3=[temp1] // restore ar.lc
764 add temp1=PT(B6), regs
767 ld8 temp3=[temp1],PT(AR_CSD)-PT(B6) // restore b6
772 ld8 temp3=[temp1],PT(AR_UNAT)-PT(AR_CSD) // restore ar.csd
777 ld8 temp3=[temp1] // restore ar.unat
778 add temp1=PT(AR_CCV)-PT(AR_UNAT), temp1
784 ld8 temp3=[temp1],PT(F6)-PT(AR_CCV) // restore ar.ccv
789 ldf.fill f6=[temp1],PT(F8)-PT(F6)
792 ldf.fill f8=[temp1],PT(F10)-PT(F8)
795 ldf.fill f10=[temp1]
801 add temp1=SOS(SAL_RA), regs
804 ld8 r12=[temp1],16 // sal_ra
807 ld8 r22=[temp1],16 // pal_min_state, virtual
810 ld8 r16=[temp1],16 // prev_IA64_KR_CURRENT_STACK
813 ld8 temp3=[temp1],16 // cr.isr
818 ld8 temp3=[temp1],16 // cr.itir
823 ld8 temp3=[temp1] // cr.iim
825 add temp1=SOS(OS_STATUS), regs
832 ld8 r8=[temp1] // os_status
901 GET_IA64_MCA_DATA(temp1)
904 add temp2=temp2, temp1 // struct ia64_sal_os_state.pal_min_state on MCA or INIT stack
905 add regs=regs, temp1 // struct pt_regs on MCA or INIT stack
911 dep temp1=-1,ms,62,2 // set region 6
914 st8 [temp2]=temp1 // pal_min_state, virtual
955 LOAD_PHYSICAL(p0,temp1,1f)
959 mov cr.iip=temp1
967 add temp1=PT(LOADRS), regs
969 ld8 temp2=[temp1],PT(AR_BSPSTORE)-PT(LOADRS) // restore loadrs
971 ld8 temp3=[temp1],PT(AR_RNAT)-PT(AR_BSPSTORE) // restore ar.bspstore
975 ld8 temp4=[temp1] // restore ar.rnat
1004 GET_IA64_MCA_DATA(temp1)
1006 add r12=temp1, temp3 // kernel stack pointer on MCA/INIT stack
1007 add r13=temp1, r3 // set current to start of MCA/INIT stack
1008 add r20=temp1, r3 // physical start of MCA/INIT stack
1055 #undef temp1