Lines Matching refs:vector
16 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
17 * allocation PCI to vector mapping, shared PCI
34 * interrupt, vector, etc.)
62 * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then
68 * IA-64 interrupt vector number <-> IRQ number mapping. On smaller
69 * systems, we use one-to-one mapping between IA-64 vector and IRQ. A
71 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
76 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
118 * vector.
123 * same vector */
133 struct list_head rtes; /* RTEs using this vector (empty =>
135 int count; /* # of RTEs that shares this vector */
193 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
228 set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
237 DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
239 rte = gsi_vector_to_rte(gsi, vector);
245 pol = iosapic_intr_info[vector].polarity;
246 trigger = iosapic_intr_info[vector].trigger;
247 dmode = iosapic_intr_info[vector].dmode;
256 if (irq_to_vector(irq) == vector) {
269 vector);
276 iosapic_intr_info[vector].low32 = low32;
277 iosapic_intr_info[vector].dest = dest;
524 int i, vector = -1, min_count = -1;
540 vector = i;
546 return vector;
550 * if the given vector is already owned by other,
551 * assign a new vector for the other and make the vector available
554 iosapic_reassign_vector (int vector)
558 if (!list_empty(&iosapic_intr_info[vector].rtes)) {
562 printk(KERN_INFO "Reassigning vector %d to %d\n",
563 vector, new_vector);
564 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
567 list_move(iosapic_intr_info[vector].rtes.next,
569 memset(&iosapic_intr_info[vector], 0,
571 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
572 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
617 static inline int vector_is_shared (int vector)
619 return (iosapic_intr_info[vector].count > 1);
623 register_intr (unsigned int gsi, int vector, unsigned char delivery,
644 rte = gsi_vector_to_rte(gsi, vector);
658 list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes);
659 iosapic_intr_info[vector].count++;
662 else if (vector_is_shared(vector)) {
663 struct iosapic_intr_info *info = &iosapic_intr_info[vector];
672 iosapic_intr_info[vector].polarity = polarity;
673 iosapic_intr_info[vector].dmode = delivery;
674 iosapic_intr_info[vector].trigger = trigger;
681 idesc = irq_desc + vector;
685 "%s: changing vector %d from %s to %s\n",
686 __FUNCTION__, vector,
694 get_target_cpu (unsigned int gsi, int vector)
701 * In case of vector shared by multiple RTEs, all RTEs that
702 * share the vector need to use the same destination CPU.
704 if (!list_empty(&iosapic_intr_info[vector].rtes))
705 return iosapic_intr_info[vector].dest;
722 if (cpe_vector > 0 && vector == IA64_CPEP_VECTOR)
748 /* Use vector assignment to distribute across cpus in node */
749 cpu_index = vector % num_cpus;
784 int vector, mask = 1, err;
797 vector = gsi_to_vector(gsi);
798 if (vector > 0) {
799 rte = gsi_vector_to_rte(gsi, vector);
802 return vector;
807 /* If vector is running out, we try to find a sharable vector */
808 vector = assign_irq_vector(AUTO_ASSIGN);
809 if (vector < 0) {
810 vector = iosapic_find_sharable_vector(trigger, polarity);
811 if (vector < 0)
815 spin_lock_irqsave(&irq_desc[vector].lock, flags);
819 if (list_empty(&iosapic_intr_info[vector].rtes))
820 free_irq_vector(vector);
822 spin_unlock_irqrestore(&irq_desc[vector].lock,
827 dest = get_target_cpu(gsi, vector);
828 err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
832 spin_unlock_irqrestore(&irq_desc[vector].lock,
838 * If the vector is shared and already unmasked for
841 low32 = iosapic_intr_info[vector].low32;
842 if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK))
844 set_rte(gsi, vector, dest, mask);
847 spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
849 printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
852 cpu_logical_id(dest), dest, vector);
854 return vector;
861 int irq, vector, index;
880 vector = irq_to_vector(irq);
886 if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
898 low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
904 iosapic_intr_info[vector].count--;
910 trigger = iosapic_intr_info[vector].trigger;
911 polarity = iosapic_intr_info[vector].polarity;
912 dest = iosapic_intr_info[vector].dest;
915 " vector %d unregistered\n",
918 cpu_logical_id(dest), dest, vector);
920 if (list_empty(&iosapic_intr_info[vector].rtes)) {
922 BUG_ON(iosapic_intr_info[vector].count);
933 memset(&iosapic_intr_info[vector], 0,
935 iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
936 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
945 /* Free the interrupt vector */
946 free_irq_vector(vector);
964 int vector, mask = 0;
969 vector = iosapic_vector;
971 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
972 * we need to make sure the vector is available
974 iosapic_reassign_vector(vector);
978 vector = assign_irq_vector(AUTO_ASSIGN);
979 if (vector < 0)
984 vector = IA64_CPE_VECTOR;
994 register_intr(gsi, vector, delivery, polarity, trigger);
998 " vector %d\n",
1002 cpu_logical_id(dest), dest, vector);
1004 set_rte(gsi, vector, dest, mask);
1005 return vector;
1016 int vector;
1019 vector = isa_irq_to_vector(isa_irq);
1021 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
1023 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
1026 cpu_logical_id(dest), dest, vector);
1028 set_rte(gsi, vector, dest, 1);
1034 int vector;
1036 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) {
1037 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
1039 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);