Lines Matching defs:R5
92 R5 = 0;
112 R5 += 1;
113 CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
129 R5 = [P4]; /* Control Register*/
130 BITCLR(R5,ENICPLB_P);
134 [P4] = R5;
256 /* P4 points to IMEM_CONTROL, and R5 contains its old
260 BITSET(R5,ENICPLB_P);
264 [P4] = R5;
299 R5 = [P4];
308 CC = BITTST(R5, 16); /* ensure it was a write*/
315 R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/
334 CC = BITTST(R5, 17); /* 0==was user, 1==was super*/
335 R5 = CC;
336 R2 <<= R5; /* if was super, check write in super mode*/
373 R5 = [P4];
374 BITCLR(R5,ENDCPLB_P);
378 [P4] = R5;
581 * points to DMEM_CONTROL, and R5 is the value we
585 BITSET(R5,ENDCPLB_P);
588 [P4] = R5;