Lines Matching defs:dsor
212 int dsor;
215 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
217 if (unlikely(clk->rate == clk->parent->rate / dsor))
219 clk->rate = clk->parent->rate / dsor;
227 int dsor;
237 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
240 if (unlikely(clk->rate == clk->parent->rate / dsor))
242 clk->rate = clk->parent->rate / dsor;
342 unsigned dsor;
345 * freq = 96MHz / dsor
347 * RATIO_SEL range: dsor <-> RATIO_SEL
348 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
349 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
350 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
353 for (dsor = 2; dsor < 96; ++dsor) {
354 if ((dsor & 1) && dsor > 8)
356 if (rate >= 96000000 / dsor)
359 return dsor;
383 unsigned dsor;
386 dsor = calc_ext_dsor(rate);
387 clk->rate = 96000000 / dsor;
388 if (dsor > 8)
389 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
391 ratio_bits = (dsor - 2) << 2;
406 unsigned dsor;
415 dsor = (ratio_bits - 6) * 2 + 8;
417 dsor = ratio_bits + 2;
419 clk-> rate = 96000000 / dsor;