Lines Matching defs:uengine
21 #include <asm/hardware/uengine.h>
59 static void *ixp2000_uengine_csr_area(int uengine)
61 return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
72 u32 ixp2000_uengine_csr_read(int uengine, int offset)
79 uebase = ixp2000_uengine_csr_area(uengine);
91 void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
97 uebase = ixp2000_uengine_csr_area(uengine);
119 void ixp2000_uengine_set_mode(int uengine, u32 mode)
126 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
131 ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
136 ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
137 ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
138 ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
147 static void ustore_write(int uengine, u64 insn)
159 ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
160 ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
163 void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
170 ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
181 ustore_write(uengine, insn);
193 addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
196 ustore_write(uengine, 0xf0000c0300ULL);
202 ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
206 void ixp2000_uengine_init_context(int uengine, int context, int pc)
211 ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
216 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
217 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
222 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
226 void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
233 mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
235 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
239 void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
247 mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
249 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
369 static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
413 ixp2000_uengine_load_microcode(uengine, ucode, 513);
414 ixp2000_uengine_init_context(uengine, 0, 0);
415 ixp2000_uengine_start_contexts(uengine, 0x01);
419 status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
423 ixp2000_uengine_stop_contexts(uengine, 0x01);
432 int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
439 if (!(ixp2000_uengine_mask & (1 << uengine)))
442 ixp2000_uengine_reset(1 << uengine);
443 ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
444 if (set_initial_registers(uengine, c))
446 ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
449 ixp2000_uengine_init_context(uengine, ctx, 0);
458 int uengine;
499 for (uengine = 0; uengine < 32; uengine++) {
500 if (ixp2000_uengine_mask & (1 << uengine)) {
501 ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
502 ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);