Lines Matching refs:vulp
190 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
191 *(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
225 *(vulp)T2_HAE_3 = t2_cfg;
242 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
243 *(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
276 *(vulp)T2_HAE_3 = t2_cfg;
333 *(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */
335 *(vulp)T2_WMASK1 = temp;
336 *(vulp)T2_TBASE1 = 0;
341 *(vulp)T2_WBASE1,
342 *(vulp)T2_WMASK1,
343 *(vulp)T2_TBASE1);
360 *(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */
362 *(vulp)T2_WMASK2 = temp;
363 *(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;
371 *(vulp)T2_WBASE2,
372 *(vulp)T2_WMASK2,
373 *(vulp)T2_TBASE2);
382 printk("%s: HAE_2 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_2);
383 printk("%s: HAE_3 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_3);
384 printk("%s: HAE_4 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_4);
385 printk("%s: HBASE was 0x%lx\n", __FUNCTION__, *(vulp)T2_HBASE);
388 *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
390 *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
396 t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1;
397 t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1;
398 t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1;
399 t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2;
400 t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2;
401 t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2;
404 t2_saved_config.hae_2 = *(vulp)T2_HAE_2;
405 t2_saved_config.hae_3 = *(vulp)T2_HAE_3;
406 t2_saved_config.hae_4 = *(vulp)T2_HAE_4;
407 t2_saved_config.hbase = *(vulp)T2_HBASE;
425 temp = *(vulp)T2_IOCSR;
429 *(vulp)T2_IOCSR = temp | (0x1UL << 26);
431 *(vulp)T2_IOCSR; /* read it back to make sure */
461 *(vulp)T2_HBASE = 0x0; /* Disable HOLES. */
464 *(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */
465 *(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */
466 *(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */
477 *(vulp)T2_HAE_4 = 0; mb();
486 *(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase;
487 *(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask;
488 *(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase;
489 *(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase;
490 *(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask;
491 *(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase;
494 *(vulp)T2_HAE_1 = srm_hae;
495 *(vulp)T2_HAE_2 = t2_saved_config.hae_2;
496 *(vulp)T2_HAE_3 = t2_saved_config.hae_3;
497 *(vulp)T2_HAE_4 = t2_saved_config.hae_4;
498 *(vulp)T2_HBASE = t2_saved_config.hbase;
500 *(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */
508 t2_iocsr = *(vulp)T2_IOCSR;
511 *(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28);
513 *(vulp)T2_IOCSR; /* read it back to make sure */
516 *(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28);
518 *(vulp)T2_IOCSR; /* read it back to make sure */
538 *(vulp)T2_CERR1 |= *(vulp)T2_CERR1;
539 *(vulp)T2_PERR1 |= *(vulp)T2_PERR1;